Device for controlling access to a computer memory

Details Device for controlling access to a computer memory Device for controlling access to a computer memory

1984-12-21

1987-06-30

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1200

Patent

active

046775447

ABSTRACT:
While a first access request signal is sent to a memory for a first data of a first data element number of leading through trailing elements, a register (12) holds a trailing address which is assigned to a memory unit for the trailing element. Responsive to a second access request signal for a second data, a difference calculator (13, 14) calculates a difference between the trailing address and a leading address which is assigned to a memory unit for the leading element of the second data. While the first access request signal is sent to the memory, another register (15) holds a reference number that is equal to a memory unit cycle time during which each memory unit is rendered busy by each access request signal. After disappearance of the first access request signal, the reference number is reduced one per clock cycle. A comparator (17, 18) compares the difference with the reference number to produce an access enabling signal which enables delivery of the second access request signal to the memory when the reference number becomes not greater than the difference taking into consideration the number of memory units accessed in each clock cycle.

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patent: 4435765 (1984-03-01), Uchida et al.
patent: 4490786 (1984-12-01), Nokatani
Cray Research, Inc., "Cray-1 S Series Hardware Reference Manual", Pub. No. HR-0808, 1981.

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