Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
2001-03-27
2004-12-21
Phu, Phoung (Department: 2631)
Pulse or digital communications
Receivers
Angle modulation
C375S330000, C375S329000, C375S283000
Reexamination Certificate
active
06834089
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90203104, filed Mar. 3, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a quadrant phase shift keying (QPSK) decoder. More particularly, the present invention relates to a device for computing tangent angles and an associated differential-encoding quadrant phase shift keying (DQPSK) decoder.
2. Description of Related Art
A conventional cable-connected transmissions system is low in mobility and short in communication distance. Therefore, many types of wireless communication techniques have been developed. Amongst wireless transmission systems, the most common one is the spread spectrum technique for transmitting voice or images. To eliminate as much interference as possible, a pseudo-noise sequence (PN) is often added to the system. Such spread spectrum techniques can be classified into two major types; namely, the frequency-hopping spread spectrum (FHSS) technique and the direct-sequence spread spectrum (DSSS) technique.
The advantages of employing the DSSS techniques in a wireless communication system include data privacy, flexibility comparison rules for the system (a soft-limited system), anti-jamming and fading rejection. However, a chip using the DSSS technique requires a large number of logic gates. Hence, a large section of the chip needs to be set aside for housing the logic gates and the chip tends to consume a large amount of energy. To resolve these problems, a digital receiver having a differential-encoding quadrant phase shift keying (DQPSK) device to serve as encoder and decoder and a matched filter using low-power pointer access memory (PAM) is used. Although such an additional component may attenuate the power consumption of the chip and area requirement in a chip slightly, the digital receiver also uses a decode/encoder having a coordinate system divided into eight quadrants. Therefore, operations demanded by the DSSS digital receiver are quite complicated. Such complications cancel out most of the advantages obtained by having fewer logic gates and lower power consumption.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a device for computing tangent angles and associated differential-encoding quadrant phase shift keying (DQPSK) decoder such that the degree of complexity in operation is greatly reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a device for computing tangent angles. The tangent computing device includes a signal input terminal, a direct current input terminal, a plurality of subtractors, a plurality of comparators, a plurality of multiplexers, an eight-bit divider, a shift encoder, an XOR logic gate and an angle-computing device. The signal-input terminal includes a real part coefficient and an imaginary part coefficient for representing a complex number signal. The direct current input terminal receives a direct current signal. The positive input terminal of a first real part subtractor receives the direct current signal and the negative input terminal of the first real part subtractor receives the real coefficient. The subtraction result is output from the output terminal of the first real part subtractor. Similarly, the negative input terminal of a second real part subtractor receives the direct current signal and the positive input terminal of the second real part subtractor receives the real coefficient. The subtraction result is output from the output terminal of the second real part subtractor. The positive input terminal of a first imaginary part subtractor receives the direct current signal and the negative input terminal of the first imaginary part subtractor receives the imaginary coefficient. The subtraction result is output from the output terminal of the first imaginary part subtractor. Similarly, the negative input terminal of a second imaginary subtractor receives the direct current signal and the positive input terminal of the second imaginary part subtractor receives the imaginary coefficient. The subtraction result is output from the output terminal of the second imaginary part subtractor. A first comparator compares the direct current signal and the real part coefficient and outputs a real part label. A second comparator compares the direct current signal and the imaginary part coefficient and outputs an imaginary part label. A first multiplexer outputs an absolute real part value of the data from the first real part subtractor or the absolute value of the data from the second real part subtractor according to the real part label. Similarly, a second multiplexer outputs an absolute imaginary part value of the data from the first imaginary part subtractor or the absolute value of the data from the second imaginary part subtractor according to the imaginary part label. The XOR logic gate receives the real part label and the imaginary part label and outputs a logically XORed result. A third multiplexer receives the absolute real part value and the absolute imaginary part value. The third multiplexer outputs the absolute real part value or the absolute imaginary part value as a horizontal axis value according to the result produced by the XOR logic gate. A fourth multiplexer also receives the absolute imaginary part value and the absolute real part value. The fourth multiplexer outputs the absolute real part value or the absolute imaginary part value as a vertical axis value according to the result produced by the XOR logic gate. The eight-bit divider produces a tangent value by dividing the vertical axis value by the horizontal axis value. The shift encoder produces a set of shift-encoded signals according to the real part label and the imaginary part label. The angle-computing device produces quantized angular values according to the tangent value and the shift-encoded groups.
This invention also provides a DQPSK decoder to be used in conjunction with a tangent computation device. The DQPSK decoder receives the quantized angular value from the aforementioned angle-computing device and performs a decoding of the complicated signals from the DSSS receiver according to the quantized angular value.
In this invention, an eight-bit divider is used inside the tangent computation device. This reduces the degree of complexity in computation for a given degree of accuracy. Furthermore, the deployment of an encoder with four-quadrant encoding simplifies the encoding procedure considerably when compared with the conventional eight-quadrant encoding technique.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Hsu Terng-Yin
Kuo Fan-Ming
Lee Chen-Yi
J.C. Patents
Macronix International Co. Ltd.
Phu Phoung
LandOfFree
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