Device for clamping multiple signals

Details Device for clamping multiple signals Device for clamping multiple signals

2001-05-29

2002-12-10

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S155000

Reexamination Certificate

active

06492921

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a device for clamping multiple signals, and more particularly a digital clamping device, which suppresses a direct-current shift in a video signal, or the like.
BACKGROUND ART
A configuration a conventional analog clamping device is illustrated in a circuit diagram of FIG.
6
. The configuration of the analog clamping device of
FIG. 6
will be described. The base of a PNP transistor Tr
2
(hereinafter referred to as “Tr
2
”) and the collector of an NPN transistor Tr
1
(hereinafter referred to as “Tr
1
”) are connected to an input terminal
1
via a condenser C
1
. The base of Tr
1
is connected to a clamp pulse supply terminal
2
via a resistor R
1
, and is connected to the emitter of Tr
1
via a resistor R
2
. The emitter of Tr
1
is connected to a reference voltage supply terminal
3
from a reference resistor of an A/D conversion section (not shown), and is grounded via a condenser C
2
. The emitter of Tr
2
is connected to an output terminal
4
, and is connected to a Vcc voltage application terminal
5
via a resistor R
3
, and the collector of Tr
2
is grounded.
Next, the outline of the operation will be described using waveform diagrams illustrated in
FIG. 7
for the respective sections in FIG.
6
. That is, a reference voltage is supplied to the emitter of Tr
1
from the reference voltage supply terminal
3
, and a clamp pulse which is as illustrated in FIG.
7
(
b
) with respect to one line of video signal is supplied to the base of Tr
1
from the clamp pulse supply terminal
2
. Tr
1
operates only when the clamp pulse is at an “H”level and, during the operation, the collector voltage of Tr
1
is applied to the base of Tr
2
, thereby performing a clamping operation at a pedestal level PL of a video signal as illustrated in FIG.
7
(
a
) which is supplied to the input terminal
1
. Note that in FIG.
7
(
a
), HD denotes a horizontal synchronization signal.
However, the conventional configuration as described above has a problem that when the power supply voltage Vcc shifts, the clamp voltage itself also shifts following the power supply voltage. Moreover, there is also a problem that due to a variation error in the reference resistance in the A/D conversion section which is not shown, the reference voltage supplied to the reference voltage supply terminal
3
shifts, whereby the pedestal level PL of the video signal shifts.
Moreover, the conventional configuration as described above also has a problem that it is difficult to finely adjust the clamp level because only one type of bias adjustment is performed.
Moreover, the conventional configuration as described above also has a problem that it uses one A-D conversion circuit for one input terminal
1
, so that for multiple analog signal inputs, it requires the same number of A-D conversion circuits as the number of input signals, thereby increasing the circuit scale accordingly.
The present invention has been made to solve the above-described problems in the prior art, and has an object to provide a device for clamping multiple signals in which the precision in controlling the clamp level is increased and which is capable of finely adjusting the amount of shift with respect to a digital reference value. Moreover, the present invention also has an object to reduce the circuit scale by using a single A/D conversion circuit in a shared manner when clamping a large number of analog signals individually.
DISCLOSURE OF THE INVENTION
In order to achieve the objects described above, a device for clamping multiple signals according to the present invention includes: input means to which an analog signal is input and which cuts off a direct-current component of the analog signal by a capacitor; A-D conversion means for converting the analog signal, whose direct-current component has been cut off by the capacitor, into a digital signal; comparison means for comparing the digital signal, which has been obtained through conversion by the A-D conversion means, with a digital reference value having g a predetermined value; a current source for adjusting a clamp level of the analog signal; and control means for controlling the current source based on a digital signal which is obtained as a result of the comparison by the comparison means.
Moreover, in accordance with the present invention the comparison means outputs a digital shift amount signal, which is an amount of shift in the digital signal obtained through conversion by the A-D conversion means with respect to the digital reference value; and the current source includes a plurality of transistors having different output levels, and the plurality of transistors are controlled by the digital shift amount signal which is output from the comparison means.
Furthermore, in one embodiment, the present invention includes: input means to which a plurality of analog signals are input and which cuts off direct-current components of the plurality of analog signals by a plurality of capacitors; time division multiplexing means for time-division-multiplexing the plurality of analog signals, whose direct-current components have been cut off by the plurality of capacitors, by using an analog switch; one A-D conversion means for converting an analog signal, which has been obtained through time division multiplexing by the time division multiplexing means, into a digital signal; signal separation means for separating the digital signal, which has been obtained through conversion by the A-D conversion means, so as to respectively correspond to the plurality of analog signals input to the input means; switching control means for controlling the analog switch and the signal separation means; comparison means for comparing a plurality of digital signals, which have been obtained through separation by the signal separation means, with a plurality of digital reference values each having a predetermined value; a current source for individually adjusting clamp levels of the plurality of analog signals input to the input means; and control means for controlling the current source based on a digital signal obtained as a result of the comparison by the comparison means.
In addition, in one embodiment, the present invention includes: input means to which a plurality of analog signals are input and which cuts off direct-current components of the plurality of analog signals by a plurality of capacitors; time division multiplexing means for time-division-multiplexing the plurality of analog signals, whose direct-current components have been cut off by the plurality of capacitors, by using an analog switch; one A-D conversion means for converting an analog signal, which has been obtained through time division multiplexing by the time division multiplexing means, into a digital signal; signal separation means for separating the digital signal, which has been obtained through conversion by the A-D conversion means, so as to respectively correspond to the plurality of analog signals input to the input means;
switching control means for controlling the analog switch and the signal separation means; comparison means for comparing a plurality of digital signals, which have been obtained through separation by the signal separation means, with a plurality of digital reference values each having a predetermined value; a current source for individually adjusting clamp levels of the plurality of analog signals input to the input means; and control means for controlling the current source based on a digital signal obtained as a result of the comparison by the comparison means.
Moreover, in one embodiment, the control means generates a control signal which turns ON a transistor having a high output level, or a large number of transistors, among those included in the current source if the digital shift amount signal output from the comparison means is high; generates a control signal which turns ON a transistor having a low output level, or a small number of transistors, if the digital shift amount signal is low; and turns OFF all of the transistors included in the curre

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