Device for calculating the parity bits of a sum of two numbers

Details Device for calculating the parity bits of a sum of two numbers Device for calculating the parity bits of a sum of two numbers

1989-02-17

1990-09-18

Smith, Jerry

Excavating

364738, G06F 1110

Patent

active

049583530

ABSTRACT:
A system as proposed for calculating the parity bits (PS) of a sum (S) of two numbers (A, B). One parity bit (PA, PB, PS) is associated with each group of m bits (a.sub.i, b.sub.i, s.sub.i) extracted from the numbers (A, B) and the sum (S). For each group, one system for calculating the parity bit (PC) associated with the corresponding group extracted from the carry word formed at the time of the addition is provided. This system includes the following:
a first stage (11) for calculating, for every i included between 1 and m-1, the values:

REFERENCES:
patent: 3925647 (1975-12-01), Louie
Fujiwara, E. et al., "Fault-Tolerant Arithmetic Logic Unit Using Parity-Based Codes", Trans. IECE Japan, vol. 64E, No. 10, Oct. 1981, pp. 653-660.

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