Device for calculating parity bits associated with a sum of two

Details Device for calculating parity bits associated with a sum of two Device for calculating parity bits associated with a sum of two

1996-09-16

1997-11-18

Ngo, Chuong D.

Boots, shoes, and leggings

G06F 1100

Patent

active

056894511

ABSTRACT:
In an adder that finds the sum of two binary numbers A and B, it is now conventional to associate one or more parity bits (PA, PB, PS) with each of the two numbers A and B and the result S. Each number A and B and the result S is divided into K groups each of m bits, and one parity bit is associated with each group. In accordance with the invention, the parity PS associated with the result S is obtained at the same time as the result. The input carry bit c.sub.i n intervening in the addition is available before the beginning of operations. Consequently, it is used in a first stage 10' upstream of the device, which calculates intermediate variables p.sub.i,j and g.sub.i,j. The other input carry bits c.sub.i,1 corresponding to the other groups are determined only later by a carry look ahead circuit, and consequently they are used only in a second stage 50' downstream of the device. The use of c.sub.i n in the first stage 10' makes it possible to perform the calculation of the parity bits and look ahead for the carry bits with a single circuit present in a third stage 60, which is intermediate between the first stage 10' and the second stage 50'.

REFERENCES:
patent: 3925647 (1975-12-01), Louie
patent: 4879675 (1989-11-01), Brodnax
patent: 4924423 (1990-05-01), Vassiliadis et al.
patent: 4958353 (1990-09-01), Greiner et al.

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