Device for avoiding parasitic capacitance in an integrated...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip

Reexamination Certificate

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Details

C257SE23019, C257SE23151, C257S758000

Reexamination Certificate

active

08049340

ABSTRACT:
An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.

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patent: 2002/0043715 (2002-04-01), Takizawa
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patent: 2004/0227227 (2004-11-01), Imanaka et al.
patent: 2005/0037601 (2005-02-01), Hsu et al.
patent: 2005/0200022 (2005-09-01), Seto
patent: 2006/0261459 (2006-11-01), Lin et al.

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