Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1999-07-22
2003-07-08
Broda, Esq., Samuel (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S004000, C703S018000, C716S030000, C716S030000
Reexamination Certificate
active
06591233
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device for and method of simulation and, more particularly, to a device for and method of simulating an electrostatic discharge (ESD) to a semiconductor integrated circuit.
2. Description of the Background Art
An ESD applied to a semiconductor integrated circuit can impair the function of the integrated circuit or destroy the integrated circuit itself. Thus, a highly ESD-resistant device structure or circuit configuration is desired. However, it becomes more difficult to hold desired ESD resistance as semiconductor devices are reduced in size.
An ESD test which is carried out on packaged final products leads to a tendency toward an increase in time period between modifying a device structure or circuit configuration and obtaining a test result, and hence becomes a significant factor that determines a product development period. Therefore, it has been desired to use simulation to predict a modification in highly ESD-resistant device structure or circuit configuration with high precision.
With an ESD applied to a semiconductor device, the semiconductor device receives high voltage to reveal a pronounced shape effect which would present no problem at normal operating voltage. For example, if the gate widths of MOSFETs are not uniform but differ according to the position because of the manufacturing process, current is liable to concentrate on a position where the gate width is smaller to cause device breakdown. An ESD simulation which takes such a device shape effect into consideration has required the use of a three-dimensional device simulation. The device simulation uses a computer to determine device characteristics from the behavior of carriers in the device, based on the physical shape and impurity distribution of the device.
However, the device simulation which divides a semiconductor device structure to be analyzed into small regions called meshes and calculates the potential and carrier concentration at a node which represents each of the meshes is required to perform calculations at as numerous as not less than hundreds of thousands of nodes. Therefore, the method using the three-dimensional device simulation is disadvantageous in requiring too much time for calculations.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a simulation device comprises: to-be-analyzed block dividing means receiving a netlist defining a circuit to be simulated and for dividing a predetermined to-be-analyzed block specifying a device included in the circuit to be simulated into a plurality of to-be-analyzed sub-blocks arranged in a predetermined direction, with equivalence with the predetermined to-be-analyzed block maintained, to output a modified netlist defining a new circuit to be simulated in which the predetermined to-be-analyzed block is replaced with the plurality of to-be-analyzed sub-blocks; and circuit simulation means for performing a circuit simulation on the new circuit to be simulated which is defined by the modified netlist, wherein the to-be-analyzed block dividing means is capable of individually setting circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks.
Preferably, according to a second aspect of the present invention, the simulation device of the first aspect further comprises parameter input means for inputting an input parameter to the to-be-analyzed block dividing means, the input parameter containing information which determines the circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks, wherein the to-be-analyzed block dividing means individually sets the circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks, based on the input parameter.
Preferably, according to a third aspect of the present invention, in the simulation device of the first or second aspect, the predetermined to-be-analyzed block includes a MOS transistor which takes a resistance element into consideration, and the predetermined direction includes the direction of the gate width of the MOS transistor.
Preferably, according to a fourth aspect of the present invention, in the simulation device of the third aspect, the to-be-analyzed block dividing means establishes an electric connection between adjacent ones of the plurality of to-be-analyzed sub-blocks through a connecting resistor.
According to a fifth aspect of the present invention, a simulation device comprises: to-be-analyzed region dividing means receiving computational structure data defining a circuit structure to be simulated which is simulatable in a three-dimensional device simulation and for dividing a predetermined to-be-analyzed region having a three-dimensional structure and specifying a device included in the circuit structure to be simulated into a plurality of to-be-analyzed sub-regions arranged in a predetermined direction and each simulatable in a two-dimensional device simulation, with equivalence with the predetermined to-be-analyzed region maintained, to output modified computational structure data defining a new circuit structure to be simulated in which the predetermined to-be-analyzed region is replaced with the plurality of to-be-analyzed sub-regions; and device simulation means for performing a two-dimensional device simulation on the new circuit structure to be simulated which is defined by the modified computational structure data.
Preferably, according to a sixth aspect of the present invention, the simulation device of the fifth aspect further comprises parameter input means for inputting an input parameter to the to-be-analyzed region dividing means, the input parameter containing information which determines device simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-regions, wherein the to-be-analyzed region dividing means individually sets the device simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-regions, based on the input parameter.
Preferably, according to a seventh aspect of the present invention, in the simulation device of the fifth or sixth aspect, the predetermined to-be-analyzed region includes a MOS transistor which takes a resistance element into consideration, and the predetermined direction includes the direction of the gate width of the MOS transistor.
Preferably, according to an eighth aspect of the present invention, in the simulation device of the seventh aspect, the to-be-analyzed region dividing means establishes an electric connection between adjacent ones of the plurality of to-be-analyzed sub-regions through a connecting resistor.
According to a ninth aspect of the present invention, a method of simulation comprises the steps of: (a) reading a netlist defining a circuit to be simulated; (b) selecting a predetermined to-be-analyzed block to be divided which specifies a device out of the circuit to be simulated; (c) dividing the predetermined to-be-analyzed block into a plurality of to-be-analyzed sub-blocks arranged in a predetermined direction and individually setting circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks; (d) establishing an electric connection between the plurality of to-be-analyzed sub-blocks so as to maintain equivalence with the predetermined to-be-analyzed block, and thereafter outputting a modified netlist defining a new circuit to be simulated in which the predetermined to-be-analyzed block is replaced with the plurality of to-be-analyzed sub-blocks; and (e) performing a circuit simulation on the new circuit to be simulated which is defined by the modified netlist.
According to a tenth aspect of the present invention, a method of simulation comprises the steps of: (a) reading computational structure data defining a circuit structure to be simulated which is simulatable in a three-dimensional device simulation; (b) selecting a predetermined to-be-analyzed region to be divided, the predeter
Broda, Esq. Samuel
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
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