Device comprising lower and upper silicon layers as capacitor el

Details Device comprising lower and upper silicon layers as capacitor el Device comprising lower and upper silicon layers as capacitor el

1991-07-31

1994-08-09

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

257751, 257306, H01L 2968, H01L 2978

Patent

active

053369220

ABSTRACT:
In a semiconductor device including charge storage capacitors, each of which includes a patterned electrode having electrode side and top surfaces, a dielectric film on the side and top surfaces, and a covering electrode on the dielectric film, the patterned electrode is composed of a lower silicon layer having layer side and top surfaces and an upper silicon layer lying on the layer side and top surfaces and having the electrode side and top surfaces. The dielectric film may be in direct contact with the electrode side and top surfaces. In this event, the lower silicon layer is preferably doped to a lower concentration between 10.sup.15 and 10.sup.18 atoms per cubic centimeter and the upper silicon layer, to a higher concentration between 10.sup.18 and 10.sup.20 atoms per cubic centimeter. Alternatively, a barrier metal film may be interposed between the dielectric film and the electrode side and top surfaces. In this event, each of the lower and the upper silicon layers is preferably doped to the lower concentration. More preferably, an amorphous silicon film is preliminarily deposited on the micro-rough side and top surfaces of an underlying silicon layer to provide the upper silicon layer having smooth electrode side and top surfaces.

REFERENCES:
patent: 5079670 (1992-01-01), Tigelaar
IBM Tech. Disclosure Bulletin, "Self-Aligned Polycide Bit Line Structure" vol. 30 No. 12 May 1988 pp. 109-110.
"Novel Stacked Capacitor Cell for 64Mb DRAM", W. Wakamiya, et al., VLSI Symp., 1989, pp. 69 to 70.
"A 5-V Only 16-kbit Stacked-Capacitor MOS RAM", IEEE Transactions on Electron Devices, vol. ED-27, No. 8, Aug. 1980, pp. 1596-1601, by M. Koyanagi, et al.
"3-Dimensional Stacked Capacitor Cell for 16M and 64M Drams", IEDM Tech. Dig., 1988 pp. 592-595, T. Ema, et al.

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