Device and process with doubled capacitors

Details Device and process with doubled capacitors Device and process with doubled capacitors

1986-12-05

1989-03-07

Carroll, J.

357 236, 357 59, 357 67, 357 71, H01L 2978, H01L 2702, H01L 2348

Patent

active

048110760

ABSTRACT:
An integrated circuit including doubled capacitors (metal/dielectric/TiN/dielectric/polysilicon). This structure is preferably made using a patterned interlevel oxide
itride layer to split a polycide layer, i.e. at some locations the polycide layer has low sheet resistance and at other locations the polycide layer is vertically split to provide two layers (TiN and unsilicided polysilicon), which are separated by the interlevel oxide
itride. A double contact etch is used before the first metal interconnect layer is deposited, so that the metal makes ohmic contact to underlying silicide or silicon or TiN in some locations, and in others provides insulated metal top plates over TiN/polysilicon capacitance to provide doubled capacitors.

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