Radiant energy – Invisible radiant energy responsive electric signalling – Semiconductor system
Reexamination Certificate
1998-07-31
2001-03-13
Hannaher, Constantine (Department: 2878)
Radiant energy
Invisible radiant energy responsive electric signalling
Semiconductor system
Reexamination Certificate
active
06201248
ABSTRACT:
DESCRIPTION
1. Technical Field
The present invention relates to a device for reading a matrix of photonic detectors.
2. Prior Art
The photonic detection devices to which the invention relates are of two types:
quantal;
thermal.
In quantal detectors, the photons received by the detector are converted into electrons and/or holes according to the detection principle, which may be intrinsic (direct transition from valence band to conduction band) or extrinsic (transition between intermediate level and conduction band). Quantal detectors can be grouped into two categories:
photovoltaic detectors, whose current intensity varies according to the incident flux;
photoconductive detectors, whose resistance varies according to the incident flux.
Thermal detectors can be grouped into two categories:
resistive bolometric detectors, whose resistance varies according to the energy of the incident radiation;
diode detectors, whose current intensity varies according to the incident flux.
Quantal detectors and thermal detectors can each be assimilated to a current generator, more or less ideal, which delivers a current whose intensity varies according to the incident flux, by means of which these detectors are suitably biased.
In cameras of interest for the invention, images are produced either using linear arrays of detectors, in other words detectors located at a regular pitch in a single direction, which must be scanned, or using mosaics or matrices, in other words detectors located in a matrix, which are not scanned in the majority of cases.
Having regard to the number of detectors used in current cameras, and having regard to the pitch between detectors, it is absolutely necessary to use a specific circuit, which will hereinafter be referred to as a read circuit, for conditioning the signal delivered by the detector and multiplexing it to a small number of information processing chains.
Each detector can be implemented either directly on the read circuit or on another circuit. In the first case a monolithic component is spoken of and in the second a hybrid component since the detectors of the detection circuit are interconnected to the input stages of the read circuit by suitable technologies such as ball hybridization.
The invention relates to a read circuit architecture which is particularly suited to the reading of mosaics of:
quantal detectors implemented on a substrate other than that of the read circuit and, consequently, hybridized to this read circuit ;
thermal detectors implemented directly on the read circuit.
A description will now be given of several read circuits of the prior art.
Read Circuits of the Charge Transfer Device Type
Read circuits of the charge transfer device type are manufactured in specific networks enabling charge transfer devices to be implemented.
An outline diagram of these circuits is given in
FIGS. 1A and 1B
.
In each elementary point depicted in
FIG. 1A
there are found:
a switch or impedance matching device AI between a detector and an MOS capacitor;
an MOS capacitor Cpel (“Design of MOS integrated circuits” published by Eyrolles) whose inversion channel is used as a storage site;
a switch which makes it possible to control the injection of the charges stored in the elementary point into the channel of a charge transfer register;
a reset device (RAZ) for the storage site.
The multiplexing of the charges stored in the elementary points to one or more outputs is effected by means of two types of charge transfer register:
parallel registers RPj which multiplex the elementary points from a column to an input of the serial register;
the serial register or registers RS which multiplex the charges coming from the parallel registers to the output stage or stages of the read circuit.
At each frame, the inversion channel of the integration capacitor is emptied of all charge by means of the reset device. The current output by each detector in the mosaic is then integrated during the exposure time in the inversion channel of the integration capacitor.
The integrated charge Qpel
ij
in the storage capacitor Cpel of the elementary point PEL(i,j) is related to the intensity Id
ij
of the current output by the detector DET(i,j) and to the exposure time by the equation:
Qpel
ij
=Id
ij
×Texposure
All or part of the charge stored in each of these integration capacitors is then taken off by means of different techniques and multiplexed by means of charge transfer devices to one or more output stages. It is in the output stage that the charges are converted into voltage by injection into a suitably biased capacitor. The voltage at the terminals of this capacitor is read by a voltage amplifier with a very high input impedance and a low output impedance.
The expression of the amplitude &dgr;Vs
ij
of the output voltage pulse, corresponding to a reading of the elementary point PEL(i,j), is given by the expression:
&dgr;Vs
ij
=Aq×Id
ij
×Texposure/Cs
where Cs is the charge voltage conversion factor of the output stage
and Aq the charge gain of the circuit.
These read circuits have the advantage of having an identical and synchronous exposure time for all the detectors.
On the other hand, they are not compatible with a random addressing of the detectors, which prevents the production of sub-images.
The reset device is absolutely necessary only if the entire integrated charge cannot be transferred into the parallel register.
Finally, these read circuits have the major drawback of having to be implemented in specific networks whose integration density is lower than that of conventional CMOS networks whereas the pitch of the detector mosaics is greatly reduced.
Read Circuits of the Switched Follower Type
For read circuits of the switched follower type described notably in references [1], [2] and [3] cited at the end of the description, an outline diagram is given in
FIGS. 2A and 2B
.
At the minimum, there are found in each elementary point depicted in FIG.
2
A:
a switch or impedance matching device AI between a detector DET(i,j) and an integration capacitor;
a capacitor Cpel implemented by means of an MOS transistor whose gate-source capacitance makes it possible to convert the current into voltage by integration;
a switch for reinitialising the integration capacitor at each frame, implemented by means of MOS transistors;
a voltage amplifier Apel with high input impedance which makes it possible to read the voltage at the terminals of the integration capacitor and to drive an output amplifier at low impedance;
a switch which makes it possible to switch the output of the amplifier of the elementary point onto a connection common to the elementary points in one and the same column, referred to as the column bus BCj.
The multiplexing of the column buses BCj to one or more output amplifiers As is effected by means of switches located at the ends of each column bus.
At each frame, the voltage at the terminals of the integration capacitor is first of all reinitialised by means of the reset switch. The detector current is then integrated in the integration capacitor for a period of time Texposure. At the end of the integration time, the output of the amplifier of the elementary point is switched onto the column bus and onto the output amplifier by means of the suitably sequenced switches of the elementary point and of the line multiplexer.
The expression of the voltage variation, &dgr;Vpel
ij
, at the terminals of the integration capacitor of the elementary point PEL(i,j) as a function of the current Id
ij
of the detector DET(i,j) of this elementary point is given by the expression:
&dgr;Vpel
ij
=Id
ij
×Texposure/Cpel
where Cpel is the capacitance of the storage capacitor of the elementary point.
The variation in the output voltage &dgr;Vpel
ij
corresponding to the reading of the elementary point PEL(i,j), is given by the equation:
&dgr;Vs
ij
=Apel×As×&dgr;Vpel
ij
=Apel×As×Id
ij
×Texposure/Cpel
where Apel (or respectively As) is the voltage gain of the voltage amplif
Marion Dominique
Mottin Eric
Pantigny Philippe
Anderson, Killer & Olick P.C.
Commissariat A l'Energie Atomique
Hannaher Constantine
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