Device and methods in a delay locked loop for generating quadrat

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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327160, 327161, H03L 706

Patent

active

061373257

ABSTRACT:
An inventive digital delay locked loop (DLL) for outputting at least first and second output clocks includes delay elements for receiving an input clock and outputting a first series of delayed clocks, each lagging the input clock more than its predecessor. A phase detector compares relative phases of the first output clock and the input clock and outputs count-up or count-down control signals in accordance therewith. First and second counters output respective first and second counts in response to the count-up or count-down control signals, and a first multiplexer selects and outputs the first output clock from among the first series of delayed clocks in accordance with the first count. Also, interpolation circuitry receives a portion of the first series of delayed clocks and outputs same, along with a plurality of interpolated clocks, in the form of a second series of delayed clocks, each lagging the input clock more than its predecessor. A second multiplexer then selects and outputs the second output clock from among the second series of delayed clocks in accordance with the second count. As a result, at least one of the clocks is generated with improved resolution over conventional DLLs.

REFERENCES:
patent: 5173617 (1992-12-01), Alsup et al.
patent: 5537069 (1996-07-01), Volk
patent: 5920518 (1999-07-01), Harrison et al.
patent: 5926047 (1999-07-01), Harrison
patent: 5945862 (1999-08-01), Donnelly et al.
Protopapas, Microcomputer Hardware Design, pp. 1-2, Jan. 1988.

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