Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2001-03-15
2009-08-04
Mai, Son L (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S230060
Reexamination Certificate
active
07570504
ABSTRACT:
A semiconductor memory device and a method of making and using a semiconductor memory device containing a word line design, which is used in ultra-large scale integrated (ULSI) circuits, that produces a device with a lower RC time constant than devices formed using prior art techniques. In one embodiment of the invention low resistivity metal strapping layers are attached to alternating halves of wordlines in a single memory array. The alternating pattern allows the low resistivity of the strapping layers to be utilized without introducing significant negative capacitive resistance effects due to strapping layers being too close to each other.
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Mai Son L
Micro)n Technology, Inc.
Schwegman Lundberg & Woessner, P.A.
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