Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1998-10-08
2001-02-13
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S049130, C365S052000
Reexamination Certificate
active
06188613
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to semiconductor memories and, more specifically, to devices and methods for erasing or programming memory cells in a semiconductor memory according to erase or program speeds, or other erase or program characteristics, stored for each memory cell in a “query” cell associated with each memory cell. This invention is particularly applicable to flash memories, Erasable Programmable Read Only Memories (EPROMs), and Electrically Erasable PROMs (EEPROMs), among others.
2. State of the Art
As shown in
FIG. 1
, a typical flash EEPROM cell
10
has two states, “programmed” and “erased.” The flash EEPROM cell
10
is programmed using hot electron injection, for example, by grounding a source
12
, energizing a drain
14
at 6.0 volts, and activating a wordline
16
at 12.0 volts. Under these conditions, a tapered channel
18
is induced between the source
12
and drain
14
, allowing electrons to pass from the source
12
, through the channel
18
, and to the drain
14
. Because of a strong electric field formed in the channel
18
as a result of the 6.0 volt source-drain differential, some electrons passing through the channel
18
are deflected upward and injected into a floating gate
20
through a gate oxide layer
22
. These injected electrons remain on the floating gate
20
as a non-volatile negative charge representative of a “0” bit, for example.
The flash EEPROM cell
10
is erased using Fowler-Nordheim tunneling, for example, by energizing the source
12
at 12.0 volts, grounding the wordline
16
, and allowing the drain
14
to float. Under these conditions, electrons stored on the floating gate
20
tunnel through the gate oxide layer
22
and are swept into the source
12
. This causes a partial depletion of negative charge on the floating gate
20
representative of a “1” bit, for example.
It should be noted that programming the flash EEPROM cell
10
increases its threshold voltage V
T
, because the negative charge stored on the floating gate
20
tends to repel electrons, and this, in turn, makes it necessary to apply a relatively high wordline voltage to the wordline
16
to induce the channel
18
. In contrast, erasing the flash EEPROM cell
10
decreases its threshold voltage V
T
, because the depletion of negative charge on the floating gate
20
allows a relatively low wordline voltage applied to the wordline
16
to induce the channel
18
.
The state of the flash EEPROM cell
10
is typically read by applying a wordline voltage of 5.0 volts, for example, to the wordline
16
. If the flash EEPROM cell
10
has been programmed, the 5.0 volt wordline voltage is insufficient to induce the channel
18
, so no current flows between the source
12
and the drain
14
. In contrast, if the flash EEPROM cell
10
has been erased, the 5.0 volt wordline voltage is sufficient to induce the channel
18
, so current does flow between the source
12
and the drain
14
. The state of the flash EEPROM cell
10
(i.e., is it a “1” bit or a “0” bit?) can then be determined by observing the presence or absence of current flow through the flash cell
10
.
The process described above for programming and erasing the flash EEPROM cell
10
is a somewhat simplified description of what actually occurs. In practice, it is possible to “over-erase” the flash EEPROM cell
10
, such that the floating gate
20
has a neutral or even slightly positive charge to it. If this occurs, the over-erased flash EEPROM cell
10
is always on. Because multiple flash cells are generally connected to a common digit line used for reading their state, a flash cell
10
that is always on can cause programmed flash EEPROM cells connected to the same digit line to be misread as erased flash cells. Accordingly, the flash EEPROM cell
10
is generally erased in incremental steps by erasing a small amount of charge from the flash EEPROM cell
10
, verifying the state of the flash EEPROM cell
10
by reading its state, and, if the flash EEPROM cell
10
is still in a programmed state, repeating the erasure and verification steps. This process continues until the erasure of the flash cell
10
is verified. In this way, over-erasure of the flash EEPROM cell
10
is avoided.
When programming the flash EEPROM cell
10
, verification is generally not required, because the process of programming by hot electron injection is self-limiting. Specifically, as the floating gate
20
takes on more and more negative charge during programming, the negative charge tends to disrupt the field created by the 6.0 volt differential between the source
12
and the drain
14
until, at some point, hot electron injection from the channel
18
to the floating gate
20
is no longer possible.
However, unlike the flash EEPROM cell
10
, some flash cells are multi-bit cells, which means they have more than one programmed state in addition to their erased state. Such multi-bit cells, instead, have multiple programmed states in addition to their erased state. For example, a multi-bit cell may have states such as those summarized in the following table.
TABLE 1
V
T
(volts)
Binary State of Flash Cell
1.5 to 3.0
00 (erased)
3.5 to 4.0
10 (programmed)
4.5 to 5.0
10 (programmed)
5.5 to 7.0
11 (programmed)
In such multi-bit flash cells, it is possible to overshoot a desired programmed state by injecting too much charge into the floating gate
20
. Accordingly, verification is typically used when programming such multi-bit cells to ensure that overshoot is avoided and that the cells are programmed as desired.
Unfortunately, the verification process described above, whether used in erasing or programming flash cells, tends to add a considerable amount of delay to the process of erasing or programming such cells . In fact, delay due to the time requirements of the verification process is the principal reason conventional flash EEPROMs are generally considered to be too slow for memory applications requiring fast access.
Accordingly, a variety of methods have been developed for limiting the access-time delay associated with verification during erasure or programming of flash cells. In one such method disclosed in U.S. Pat. No 5,712,815 to Bill et al., programming and verification occur at the same time, so as to eliminate the time-consuming process of switching from a relatively high voltage programming step to a separate low-voltage verification step (i.e., the process of verification involves reading the flash cells, which is a relatively low-voltage operation). Unfortunately, the Bill et al. method requires the addition of some relatively complex circuitry, and it does not eliminate the need for verification during erasure or programming but, instead, merely masks it with the programming step. In another method, disclosed in U.S. Pat. No. 5,729,489 to Fazio et al., adaptive learning techniques are used during programming to “learn” the threshold voltage V
T
programming characteristics of a representative flash cell, and these programming characteristics are then used to program other flash cells without verification. This method also requires the addition of some relatively complex circuitry, and suffers from the inaccuracies inherent in applying the programming characteristics of a representative flash cell to the process of programming other flash cells that may not have the same programming characteristics.
Therefore, there is a need in the art for an improved device and method for erasing or programming flash and other memory cells. Such a device and method should avoid the problems described above that are associated with previous methods.
SUMMARY OF THE INVENTION
An inventive system for changing the state of a memory cell (e.g., a flash cell) includes a query cell (e.g., another flash cell) that stores a value (e.g., a charge) representative of a characteristic rate of change in the state of the memory cell. The value may be, for example, an erasure or programming speed of the memory cell. When the state of the memory cell is to be changed (e.g., the memory
Le Thong
Micro)n Technology, Inc.
Nguyen Viet Q.
Trask & Britt
LandOfFree
Device and method in a semiconductor memory for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device and method in a semiconductor memory for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device and method in a semiconductor memory for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2596453