Device and method in a delay locked loop for generating...

Details Device and method in a delay locked loop for generating... Device and method in a delay locked loop for generating...

2000-03-15

2001-08-28

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000, C327S161000

Reexamination Certificate

active

06281726

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to semiconductor-based electronics and, more specifically, to devices and methods in, for example, delay locked loops for generating quadrature and other off-phase clocks. Such devices and methods are particularly applicable to synchronous semiconductor devices, such as Synchronous Dynamic Random Access Memories (SDRAMS).
2. State of the Art
As shown in
FIG. 1
, a conventional Delay Locked Loop (DLL)
10
receives an input clock CLKIN at a 0° phase and generates an output clock CLKOUT that is 180° out of phase with the input clock CLKIN.
More specifically, n Delay Elements
12
of the DLL
10
receive the input clock CLKIN and output a series of increasingly delayed clocks D
1
, D
2
, D
3
, D
4
, D
5
, . . . , D
n
. To illustrate this further, it may be the case, for example, that the delayed clocks D
1
, D
2
, D
3
, D
4
, D
5
are out of phase with the input clock CLKIN by 1°, 2°, 3°, 4°, and 5°, respectively.
In response to the count from a 1-to-n counter
14
, an n-to-1 mux (i.e., multiplexer)
16
selects one of the delayed clocks D
1
, D
2
, D
3
, D
4
, D
5
, . . . , D
n
and outputs it as the output clock CLKOUT. The counter
14
is controlled by a phase detector
18
that compares the input clock CLKIN to the output clock CLKOUT. If the output clock CLKOUT lags the input clock CLKIN by less than 180°, the phase detector
18
directs the counter
14
to Count up until the output clock CLKOUT lags the input clock CLKIN by exactly 180°. Conversely, if the output clock CLKOUT lags the input clock CLKIN by more than 180°, the phase detector
18
directs the counter
14
to count down until the output clock CLKOUT lags the input clock CLKIN by exactly 180°. Of course, “exactly” is a relative term, since the fineness of control the phase detector
18
has over the output clock CLKOUT is limited by the selection of delayed clocks D
1
, D
2
, D
3
, D
4
, D
5
, . . . D
n
available from the n Delay Elements
12
.
The DLL
10
described above generally works well for generating the 180° out of phase output clock CLKOUT. However, there is often a need to generate off-phase clocks at, for example, 90° and 270° at the same time a 180° clock is generated. Such off-phase clocks are generally referred to as “quadrature” clocks.
Accordingly, as shown in
FIG. 2
, another conventional DLL
20
is available for generating multiple clocks, including quadrature clocks. The DLL
20
receives an input clock CLKIN at a 0° phase and generates an output clock CLKOUT that is 180° out of phase and a quadrature clock CLKOUT that is 90° out of phase.
More specifically, x Delay Elements
22
of the DLL
20
receive the input clock CLKIN and output a series of increasingly delayed clocks D
1
, D
2
, D
3
, D
4
, D
5
, . . . , D
x
. In response to the count from a 1-to-X counter
24
, an x-to-1 mux
26
selects one of the delayed clocks D
1
, D
2
, D
3
, D
4
, D
5
. . . , D
x
and outputs it as the quadrature clock CLKOUT at 90°. At the same time, x Delay Elements
28
receive the quadrature clock CLKOUT at 90° and output a series of increasingly delayed clocks D
x+1
, D
x+2
, D
x+3
, D
x+4
, D
+5
, . . . , D
2x
. In response to the count from another 1-to-x counter
30
, another x-to-1 mux
32
selects one of the delayed clocks D
x+1
, D
x+2
, D
x+3
, D
x+4
, D
x×5
, . . . , D
2x
and outputs it as the output clock CLKOUT at 180°.
The counters
24
and
30
) are controlled by a phase detector
34
that compares the input clock CLKIN at 0° to the output clock CLKOUT at 180°. If the output clock CLKOUT lags the input clock CLKIN by less than 180°, the phase detector
34
directs the counters
24
and
30
to count up until the output clock CLKOUT lags the input clock CLKIN by exactly 180°. Conversely, if the output clock CLKOUT lags the input clock CLKIN by more than 180°, the phase detector
34
directs the counters
24
and
30
to count down until the output clock CLKOUT lags the input clock CLKIN by exactly 180°. As stated above, “exactly” is a relative term, since the fineness of control the phase detector
34
has over the output clock CLKOUT is limited by the selection of delayed clocks available from the n Delay Elements
22
and
28
.
The DLL
20
described above thus provides multiple clocks, including quadrature clocks. However, the output clock CLKOUT generated by the DLL
20
has one-half the resolution of the output clock CLKOUT generated by the DLL
10
(FIG.
1
). An example will illustrate this. Suppose that the change in phase between successive delayed clocks output by the Delay Elements
12
(FIG.
1
),
22
, and
28
is 1°. As a result, the output clock CLKOUT generated by the DLL
10
(
FIG. 1
) is accurate to within 1°, while the output clock CLKOUT generated by the DLL
20
is only accurate to within 2°. Such a reduction in resolution does not provide acceptable performance for today's high-speed electronics.
Therefore, there is a need in the art for devices and methods in, for example, delay locked loops for generating quadrature and other off-phase clocks with improved resolution.
SUMMARY OF THE INVENTION
A device for generating first and second output signals (e.g., output clocks), each of which lags an input signal (e.g., an input clock) by a controlled amount different than the other, includes circuitry (e.g., delay elements and interpolation circuitry) for receiving the input signal and outputting first and second series of delayed signals. “A controlled amount” of lag refers to, for example, an amount of time or a number of degrees or radians. Each delayed signal in each series lags the input signal more than its predecessor in its respective series, and the second series includes a portion of the first series and a plurality of signals interpolated therefrom. Circuitry (e.g., a phase detector) for comparing relative phases of at least one of the first and second output signals with the input signal outputs control signals (e.g., count-up and count-down control signals) in accordance with the comparison. Additional circuitry (e.g., counters and multiplexers) then responds to the control signals by selecting and outputting the first and second output signals from among the respective first and second series of delayed signals.
In other embodiments of this invention, the device described above is incorporated into a Synchronous Dynamic Random Access Memory (SDRAM) and an electronic system (e.g., a computer system), and is fabricated on the surface of a semiconductor substrate, such as a wafer.
In another embodiment of this invention, a delay locked loop (DLL) for outputting at least first and second output clocks includes a plurality of delay elements for receiving an input clock and outputting a first series of delayed clocks, each lagging the input clock more than its predecessor. A phase detector compares relative phases of the first output clock and the input clock and outputs control signals in accordance therewith. First and second counters output respective first and second counts in response to the control signals, and a first multiplexer selects and outputs the first output clock from among the first series of delayed clocks in accordance with the first count. Also, interpolation circuitry receives a portion of the first series of delayed clocks and outputs same, along with a plurality of interpolated clocks, in the form of a second series of delayed clocks, each lagging the input clock more than its predecessor. A second multiplexer then selects and outputs the second output clock from among the second series of delayed clocks in accordance with the second count.
In still another embodiment, first and second output signals are generated, each lagging an input signal by a controlled amount different than the other. Specifically, first and second series of delayed signals are generated, each lagging the input signal more than its predecessor, with the second series including a portion of the first series and a plurality of si

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