Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-02-15
2004-01-06
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S233100
Reexamination Certificate
active
06674666
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device and method for timing the reading a nonvolatile memory with reduced switching noise. In particular, the present invention is used in a flash memory adopting the FWH/LPC (Firm Ware Hub/Low Pin Count) protocol, without being limited thereto.
2. Description of the Related Art
As is known, in traditional flash memories that implement an asynchronous sensing solution, all timings are generated starting from delays which are preset and which can possibly be adjusted through appropriate configuration circuits. Configurability is particularly necessary in processes that are still to be completely characterized and for which, consequently, the variability of each process parameter is not known for certain.
For a better understanding of the problems overcome by the present invention, see
FIG. 1
, which shows a simplified block diagram of a memory device
1
formed by a flash memory using an FWH/LPC (Firm Ware Hub/Low Pin Count) protocol. The diagram of
FIG. 1
thus comprises both the components proper to a flash memory and the components belonging to an FWH interface.
The memory device
1
of
FIG. 1
comprises a memory array
2
, a sensing stage
3
, an output stage
4
, a timing stage
5
, a state machine
6
, an output-enable generator
7
, and an address-transition sensing stage
8
.
In detail, the memory array
2
comprises, in a known way which is not illustrated, a plurality of memory cells, one or more reference cells, row-decoder and column-decoder stages for addressing the memory cells, and biasing, equalizing and conversion circuits for enabling reading, writing and erasing operations to be performed on the memory cells. The sensing stage
3
is connected to the outputs of the memory array
2
and comprises, in a known way, a plurality of sense amplifiers
15
a,
of which only one is shown, and a plurality of latch stages
15
b,
of which only one is shown. The output stage
4
is connected to the output of the sensing stage
3
through data switches
18
and comprises a plurality of output buffers
16
(of which only one is shown in the figure), which supply, on an output
9
of the memory, the data OUT read in the memory array
2
. In the present example of a flash memory based on the FWH/LPC protocol, the output buffers
16
have characteristics such as to be able to work on a Peripheral Component Interconnect (PCI) bus.
The state machine
6
, in a per se known manner, receives from outside an external clock signal CK and generates an internal clock signal CLK, which is supplied to the address-transition sensing stage
8
. Furthermore, the state machine
6
generates a first state signal S(X) and a second state signal S(X+1). The first state signal S(X) controls an address switch
19
connected between an address input
10
of the memory device
1
which receives the address data ADDR and a node
11
connected both to the address-transition sensing stage
8
and to the memory array
2
. The second state signal S(X+1) is supplied to the output-enable generator
7
so as to enable the latter to generate, at the appropriate instant, an output-enable signal OE, which is supplied to the output stage
4
.
The address-transition sensing stage
8
receives from outside the address data ADDR and generates an address-transition signal ATD, which is supplied to the timing stage
5
, which in turn generates, as will be described in greater detail hereinafter with reference to
FIGS. 2 and 3
, an equalizing signal EQLZ, a read signal R, a data-latching signal DL, and a sensing-latch signal SAL. In particular, and in a per se known manner, the equalizing signal EQLZ (active high) is supplied to memory array
2
to activate the array-equalizing step. The read signal R (active high) and the sensing-latch signal SAL (active low) are supplied to the sensing stage
3
so that the read signal R will activate the sense amplifiers
15
a
and then enable the sensing step, while the sensing-latch signal SAL will store, in the latches
15
b,
the data detected by the sense amplifiers
15
a.
Finally, the data-latching signal DL (active low) is supplied to the data switches
18
to prevent the data stored in the latches
15
b
from being sent to the output stage
4
during data modification.
The known timing stage
5
is implemented as shown in FIG.
2
.
In detail, the timing stage
5
comprises an equalizing control circuit
21
, receiving the address-transition signal ATD and outputting the equalizing signal EQLZ; an output-isolation control circuit
22
, receiving the equalizing signal EQLZ and outputting the data-latching signal DL; a sensing-latch control circuit
23
, receiving the data-latching signal DL and generating the sensing-latch signal SAL; and a read-enable circuit
24
, receiving the address-transition signal ATD and the sensing-latch signal SAL and outputting the read signal R.
As shown in
FIG. 3
, after the first state signal S(X) has controlled closing of the address switch
19
, when the address-transition sensing stage
8
detects switching of the input addresses, it generates a positive pulse of the address-transition signal ATD. Upon receiving this pulse, the read-enable circuit
24
causes the read signal R to switch to the high state, thus enabling reading by the sense amplifiers
15
a.
Furthermore, the equalizing control circuit
21
causes the equalizing signal EQLZ to switch to the high state, so activating the equalizing step for the memory array
2
.
After a preset delay from switching to the high state by the equalizing signal EQLZ, the output-isolation control circuit
22
causes switching to the high state of the data-latching signal DL, thus bringing about opening of the data switches
18
, and thus separating the sensing stage
3
from the output stage
4
.
At the end of the equalizing step, the sense amplifiers
15
a
detect the datum supplied by the memory array
2
.
After a preset delay from switching to the high state by the data-latching signal DL, the sensing-latch control circuit
23
generates a negative pulse of the sensing-latch signal SAL, which enables the latches
15
b
of the sensing stage
3
and causes switching to the low state of the read signal R, so terminating the reading step.
As soon as the data-latching signal DL switches back to the low state, the data switches
18
are closed again, so enabling transmission of the data to the buffers
16
of the output stage
4
.
In the known memory device
1
described above, since all the timing signals shown in
FIG. 3
are generated in an asynchronous way and are not correlated to other external events, it may happen that the sensing-latch pulse SAL is generated during switching to the low state of the output-enable signal OE, which is generated upon reception of the second state signal S(X+1). In this situation, data latching by the latches
15
b
takes place during activation of the output buffers
16
. Or else, it may happen that the sensing-latch pulse SAL is generated at any other positive edge of the internal clock signal CLK subsequent to the switching referred to above of the output-enable signal OE, and thus at a time corresponding to switching of the output buffers
16
. These conditions are illustrated in
FIG. 3
, in which the dashed line highlights the overlapping time window between the sensing-latch pulse SAL and the positive edge of the internal clock signal CLK. The foregoing is disadvantageous in so far as the switching noise of the output buffers
16
may disturb the supply lines, and thus modify the data read from the memory array
2
. This is particularly troublesome in the case of output buffers operating on PCI buses, as in the case considered, since the buses require high currents and are thus three to four times noisier than the buffers present in other types of memories. Consequently, the noise induced on the supply lines may impair reading and render the memory altogether unreliable.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention provide
Maone Alessandro Francesco
Perroni Maurizio Francesco
Iannucci Robert
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tran M.
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