Device and method for the programming of a memory

Static information storage and retrieval – Floating gate – Particular connection

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Details

36518511, 36518518, G11C 1100

Patent

active

059911999

ABSTRACT:
In a device for programming EPROM-Flash type memory cells of memory words of a memory, a bit line of a memory cell of a given rank of the first word and at least one bit line of a memory cell of the same rank in a word that is horizontally adjacent to this first word are connected together to two common programming connections by means of a bias circuit, and the bias circuit comprises two bias voltage inputs and one bias voltage output. The programming method consists in the successive programming, during different programming cycles, of the different cells of this first word and, during the same programming cycle, a different cell, of the same rank, in at least one word that is different from this first word is programmed.

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"A 16-Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation" Atsumi et al, Journal of Solid State Circuits, vol. 29 No. 4, Apr. 1994.

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