Static information storage and retrieval – Floating gate – Particular biasing
Patent
1999-03-15
2000-04-25
Nelms, David
Static information storage and retrieval
Floating gate
Particular biasing
36518518, 3651853, 36518529, G11C 1606
Patent
active
060551909
ABSTRACT:
A device and method of operation for an improved erase-verify device in which the non-selected cells, within a bit line column of an array of cells, remain inactive. Only the active cell is verified with minimum bit line column leakage associated with the operation of erase verification. Erase verification for a memory array is achieved by applying a source voltage (generally positive) to the common source line associated with a column of cells in the array. This will raise the threshold voltages of the cells (through the body effect of the semiconductor device) to a level higher than the predetermined minimum erased threshold voltage. The non-selected wordlines are coupled to a reference level below the threshold level of the cell (e.g. ground), and the selected wordline is coupled to a positive voltage which is a function of the source voltage. The source voltage is also added to the drain source voltage. The source voltage thereby serves as a feedback input to both the wordline and bit line inputs. Thereafter, a fixed drain-to-source bias is applied to the selected bit line column to conduct current for verification of the cell. The source voltage feedback allows the wordline voltage to be adjusted so that read current through the selected cell can be maintained at a desired level. Using this approach, the bit line column leakage caused by over-erased cells can be effectively suppressed, and an accurate verification result can be achieved.
REFERENCES:
patent: 5218571 (1993-06-01), Norris
patent: 5396459 (1995-03-01), Arakawa
patent: 5416738 (1995-05-01), Shrivastava
patent: 5457652 (1995-10-01), Brahmbhatt
patent: 5467306 (1995-11-01), Kaya et al.
patent: 5467310 (1995-11-01), Yoshida et al.
patent: 5537362 (1996-07-01), Gill et al.
patent: 5557569 (1996-09-01), Smayling et al.
patent: 5574686 (1996-11-01), Watsuji et al.
patent: 5581502 (1996-12-01), Richart et al.
Chiou Ming-Jye
Lo Ying-Che
Lu Wenpin
Wang Mam-Tsung
Ho Hoai V.
Macronix International Co. Ltd.
Nelms David
LandOfFree
Device and method for suppressing bit line column leakage during does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device and method for suppressing bit line column leakage during, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device and method for suppressing bit line column leakage during will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-998956