Device and method for selecting and addressing extended memory a

Details Device and method for selecting and addressing extended memory a Device and method for selecting and addressing extended memory a

1994-12-08

1997-05-06

Chan, Eddie P.

395405, 395412, G06F 1206, G06F 1210

Patent

active

056279868

ABSTRACT:
An extended memory mapping and selecting scheme for a microprocessor structured with multiple internal address lines. The internal address lines are coupled to external memory devices via a dual port RAM which enables the addresses of the external memories to be mapped and translated into the internal address lines for access by the microprocessor. The memory addressing capability is effectively enhanced by allowing the limited number of internal address lines to address larger external memories having a greater number of address locations.

REFERENCES:
patent: 4292668 (1981-09-01), Miller et al.
patent: 4296467 (1981-10-01), Nibby, Jr. et al.
patent: 4340932 (1982-07-01), Bakula et al.
patent: 4805092 (1989-02-01), Cerutti
patent: 4979144 (1990-12-01), Mizuta
patent: 5010475 (1991-04-01), Hazawa
patent: 5218684 (1993-06-01), Hayes et al.

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