Device and method for reducing power consumption within an accel

Details Device and method for reducing power consumption within an accel Device and method for reducing power consumption within an accel

1997-12-22

2000-03-21

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Interface

345504, 710126, 710129, 713320, 713322, G06F 1314

Patent

active

060408456

ABSTRACT:
A computer is provided having a bus interface unit which is coupled between a peripheral bus and a dedicated graphics bus. The graphics bus can be linked to the bus interface unit by an AGP, while the peripheral bus can be linked to the bus interface unit by a PCI. Arbitration for the AGP bus can determine when mastership is granted to an AGP master (i.e., graphics accelerator/controller). Until mastership is granted, the AGP target is powered down to a low power state where power consumption within the bus interface unit is minimal. It is not until the AGP master achieves mastership that the graphics target (core logic and memory controller) within the bus interface unit is placed in an operational (fully powered) state. The computer therefore employs a bus interface unit which can be dynamically switched from a high power state to a low power state and vice versa, depending upon accesses to the graphics target.

REFERENCES:
patent: 5721935 (1998-02-01), DeSchepper et al.
patent: 5821949 (1998-10-01), Deering
patent: 5835435 (1998-11-01), Bogin et al.
patent: 5857086 (1999-01-01), Horan et al.

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