Device and method for reducing bus activity in a computer system

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395285, 364DIG1, G06F 1200

Patent

active

055465609

ABSTRACT:
A method and device for avoiding unnecessary data broadcasts by detecting the presence of additional cache-equipped bus-masters is provided. The device includes a master bus-master equipped with a local cache arrangement for caching data originating in a system memory. The master bus-master communicates with the system memory over a bus, and is coupled to a control line at an input. Any cache-equipped slave bus masters that are caching data with the system memory are coupled to the control line by an output and are configured to generate a signal at the output to drive the control line to a predetermined state to indicate that they are caching data. The master bus-master detects the state of the control line and determines whether the data being buffered in its local cache arrangement is shared based upon the state of the control line. If the state of the control line indicates the presence of other cache-equipped bus-masters, the master bus-master automatically broadcasts data that it modifies; otherwise it writes the modified data back to the system memory when the cache space occupied by the modified data is required for new data.

REFERENCES:
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patent: 5261106 (1993-11-01), Lentz et al.
patent: 5265235 (1993-11-01), Sindhm et al.
patent: 5293384 (1994-03-01), Keeley et al.
patent: 5388224 (1995-02-01), Maskas
Al-Sadoun et al., "Cache Coherency in Multiple Bus Systems", Inter. J. Electronics, vol. 73, No. 3, Sep. 1993, pp. 497-522.

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