Device and method for reading non-volatile memories having...

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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Details

C365S230010, C365S201000, C365S233100

Reexamination Certificate

active

06975559

ABSTRACT:
The invention relates to a method for testing non-volatile memory devices that have at least one parallel communication interface, and a conventional matrix of non-volatile memory cells with respective reading, changing and erasing circuits, wherein during the testing procedure, a reading mode is entered for reading a memory location upon the rise edge of a control signal producing a corresponding ATD signal. Advantageously in the invention, a subsequent reading step is started also upon the fall edge of the control signal.In this way, at each cycle of the control signal two memory locations, instead of one as in the prior art, are read.

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