Device and method for protecting an integrated circuit during an

Details Device and method for protecting an integrated circuit during an Device and method for protecting an integrated circuit during an

1997-01-07

2000-10-10

Leja, Ronald W.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

H02H 300

Patent

active

061308110

ABSTRACT:
An integrated circuit having a voltage protection circuit in electrical communication with an input buffer of the integrated circuit and a method for providing voltage protection to the input buffer are disposed. In one exemplary embodiment, the voltage protection circuit is an active device, such as a transistor, in electrical communication with an input node of the input buffer. When the active device actuates it provides a current path which limits a potential seen at the input buffer to a value less than an electrostatic discharge (ESD) potential. In one implementation the active device responds to a voltage which develops in response to current flow in an ESD circuit, and in a further implementation it responds to a gate to source potential during an ESD event. In both implementations the active device is actuated during an ESD event and is deactuated during normal operation of the circuit. In a further exemplary embodiment an isolation circuit is interposed between a supply node of the input buffer and the input buffer. When no external power is applied to the supply node the isolation circuit is open, isolating the input buffer from the supply node. The potential of the bond pad is divided between the gate oxide of internal buffer transistors and the isolation circuit. The voltage protection circuit of the invention ensures that the input potential to the input buffer is less than a breakdown voltage of the input buffer.

REFERENCES:
patent: 5479039 (1995-12-01), Lien
patent: 5610790 (1997-03-01), Staab et al.
patent: 5729419 (1998-03-01), Lien

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