Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-08-30
2002-03-05
Leja, Ronald W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
Reexamination Certificate
active
06353521
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to integrated circuits, and more particularly to electrostatic protection circuits.
BACKGROUND OF THE INVENTION
Integrated circuits are connectable to “the outside world” through bond pads, also referred to as die terminals, die pads, or contact pads. An input buffer, often configured as an invertor, is interposed between the bond pad and active circuitry of the integrated circuit The input buffer is comprised of buffer transistors which should be protected from voltages caused by electrostatic discharge (ESD) during handling and testing of the integrated circuit. Subjecting a device to ESD is referred to as an ESD event. Typically, an ESD circuit, which is well known in the art, is connected at the bond pad. The ESD circuit is a protection device typically comprised of diodes connected back to back at the bond pad. The ESD circuit protects the buffer transistors from high voltages caused by an ESD event The ESD circuit keeps the potential of the bond pad from exceeding a maximum value.
In one application shown in
FIG. 1
, a diode
1
is interposed between the input to the input buffer
2
and a reference node
3
. During handling the integrated circuit is not connected to any electrical potentials, and the potential of the reference node
3
is floating. During an ESD event a potential difference develops across the diode
4
. If this potential difference is large enough diode
4
is reversed biased allowing the electrostatic current to shunt the active circuitry and buffer transistors of the integrated circuit However, the diode breakdown voltage may be greater than the breakdown potential of the buffer transistors.
Thus, although the ESD circuit is designed to withstand high current levels, the bond pad potential may be greater than the breakdown voltage of the buffer transistor. This is especially true for a buffer transistor fabricated using current technologies, in which case the thickness of the gate insulator of the buffer transistor has decreased from the thickness obtained using previous fabrication technologies. As the thickness of the gate insulator decreases, the breakdown voltage of the gate insulator decreases. Thus, the breakdown voltage of the buffer transistor is often below the potential established on the bond pad by the ESD circuit.
Thus, a need exists to provide a voltage protection circuit which eliminates breakdown of buffer transistors having low breakdown voltages.
SUMMARY OF THE INVENTION
The invention provides an integrated circuit having a voltage protection circuit and a method for providing voltage protection to the input buffer. The voltage protection circuit of the invention limits a potential seen at the input buffer input node to a value less than a value provided by an electrostatic discharge (ESD) circuit The input buffer is interposed between a bond pad and active circuitry of an integrated circuit.
In a first currently envisioned exemplary embodiment, an active device, such as a transistor, is interposed between an input node to the input buffer and a supply node. In one implementation the active device responds to current generated in the ESD circuit. A potential develops at a control input of the active device as a result of the current in the ESD circuit, and the active device actuates. In a further implementation of the first embodiment the potential of the control input floats during an ESD event and the active device actuates in response to the generation of. a potential on the bond pad. In both implementations the active device is deactuated during normal operation. In both implementations the actuated active device and an input resistor provide a current path and hence a voltage divider circuit to reduce the potential at the input buffer input node to a value well below the breakdown voltage of the input buffer.
In a second currently envisioned exemplary embodiment of the invention an isolation circuit is interposed between a supply node of the input buffer and the input buffer. When no external power is applied to the supply node, the isolation circuit is open isolating the input buffer from the supply node. The potential of the bond pad is divided between the gate oxide of internal buffer transistors and the isolation circuit Thus, the input buffer is protected during the ESD event.
REFERENCES:
patent: 5237395 (1993-08-01), Lee
patent: 5276582 (1994-01-01), Merrill et al.
patent: 5479039 (1995-12-01), Lien
patent: 5610790 (1997-03-01), Staab
patent: 5729419 (1998-03-01), Lien
patent: 6078487 (2000-06-01), Partovi et al.
Gans Dean
Marr Ken
Leja Ronald W.
Schwegman Lundberg Woessner & Kluth P.A.
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