Drying and gas or vapor contact with solids – Process – By centrifugal force
Reexamination Certificate
1999-07-09
2001-07-24
Wilson, Pamela (Department: 3749)
Drying and gas or vapor contact with solids
Process
By centrifugal force
C034S317000, C034S328000, C034S481000, C034S058000, C034S061000, C427S241000, C427S346000, C438S632000, C438S633000, C438S760000, C438S782000
Reexamination Certificate
active
06263586
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88110181, filed Jun. 17, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor manufacturing device and a method. More particularly, the present invention relates to a device and method for planarizing a film layer.
2. Description of Related Art
As semiconductor manufacturing passes into the deep submicron scale, dimensions of each device shrink. Hence, a higher operating speed for each integrated circuit results. For an integrated circuit with the same device layout, operating speed is closely related to density of the devices.
One major problem often encountered in metal plug fabrication, damascene processes or the deposition of a layer of dielectric material between neighboring lines or devices is the gap-filling capability of the material involved. Following the reduction of device dimensions and width of circuit lines, device density increases. In the process of filling the gaps or trenches on a silicon wafer, voids may be formed especially when the gaps or trenches are smaller than 0.1 &mgr;m.
FIG. 1
is a schematic, cross-sectional view after forming an inter-layer dielectric (ILD) layer over a substrate that has circuit lines thereon in a multi-level metallization process. As shown in
FIG. 1
, metal lines
110
are formed on a substrate
100
so that there is a gap
120
between two neighboring metal lines
110
. A dielectric layer
130
is formed over the substrate and the metal lines
110
. Due to the poor gap-filling capability of the deposited dielectric material when the dielectric layer
130
is formed, a void
140
is likely to form within the dielectric layer
130
inside the gap region
120
. The void
140
not only can lead to poor insulation, but can also enclose some corrosive chemicals that can corrode the metallic lines
110
and result in circuit problems. In addition, too much topographical height difference H after the deposition of the dielectric layer
130
is likely to affect subsequent photolithographic and etching processes as well. This is because only a highly planar surface can avoid the problems due to light diffusion during exposure so that a clear pattern is transferred.
SUMMARY OF THE INVENTION
The invention provides a method for planarizing a film layer so that voids are eliminated and topographical height differences are reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for planarizing a film layer. A film layer is deposited over a silicon wafer. The wafer is next placed inside a carrier with a front face of the wafer facing a centrifugal center. The wafer inside the carrier is heated so that the film layer becomes fluid. In the meantime, the wafer is also driven in a circular movement so that the film layer can be planarized.
The invention also provides a device for planarizing a film layer in semiconductor manufacturing. The device includes a circular track having a track surface that faces the track center, a carrier that moves along the track carrying silicon wafers around the track center, and a set of heating elements within the carrier and/or the track for heating the film layers on the wafers and making the film layers fluid.
According to this invention, silicon wafers having their front surfaces all facing the track center are placed inside the carrier. The carrier then runs on the track, and hence follows a circular path. The wafers are heated while the carrier is in motion so that the film layers on the wafers become fluid. The centrifugal force exerted on the thin films accelerate the movement of the film layer, thus planarizing the film layer and removing any voids therein.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5037777 (1991-08-01), Mele et al.
patent: 5104482 (1992-04-01), Monkowski et al.
patent: 5302233 (1994-04-01), Kim et al.
patent: 5500243 (1996-03-01), Yang
patent: 5679641 (1997-10-01), Matsuda et al.
patent: 5918152 (1999-06-01), Erzhuang et al.
patent: 5925410 (1999-07-01), Akram et al.
patent: 5928960 (1999-07-01), Green et al.
Huang Jiawei
Patents J. C.
Taiwan Semiconductor Manufacturing Co. Ltd.
Wilson Pamela
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