Static information storage and retrieval – Floating gate – Multiple values
Patent
1998-12-14
2000-09-05
Nelms, David
Static information storage and retrieval
Floating gate
Multiple values
3651852, 36518526, G11C 1604
Patent
active
061152854
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates generally to a non volatile memory device for multi-level charge storage. In particular, a device and a method for multilevel charge storage and an apparatus and a method for reading out from the storage device is disclosed.
Description of the Related Art
Non-volatile semiconductor memory devices are an important class of solid-state memory devices. A particular type of non-volatile semiconductor memory devices are flash EEPROM devices. The primary mechanism by which data are stored in a non-volatile memory device is by access to a memory cell. The demand for high-density Flash EEPROM memory devices in portable computing and telecommunication applications stimulates continuous efforts on scaling of flash EEPROM memory cell size. In order to further increase the storage capability of Flash memory devices, Multi-Level Charge Storage (MLCS) techniques have been developed. These techniques allow further reductions in the cost per bit of information of flash EEPROM non-volatile memory devices.
Typically, a MLCS memory device is configured such that 2.sup.n different charge levels, corresponding to threshold voltage levels, can be stored in one memory cell and the current corresponding to these different threshold voltage levels can be read-out. Thus, storage and read-out of n bits of data (with n being larger than or equal to two) in a single memory cell can be achieved. The cost per bit of information with MLCS techniques is reduced as a number related to 1
.
Multi-level storage or write or progammation circuits and techniques, and read-out circuits and techniques have been disclosed. U.S. Pat. No. 5,043,940 of Harrari discloses a split-channel EEPROM device that can be programmed in more than two programmable threshold states. U.S. Pat. No. 4,771,404 of Mano et al. discloses a memory device which has memory cells capable of storing ternary or more information. This memory device includes a multilevel detector for detecting the information of the memory cells at one time and a reference generator for generating reference levels therefor. U.S. Pat. No. 5,163,021 of Mehrotra et al. discloses improvements in the Circuits and Techniques for read, write and erase of Multi-State EEPROM memory devices, the improved circuits making the reading relative to a set of threshold levels as provided by a corresponding set of reference cells. U.S. Pat. No. 4,415,992 discloses a read-out scheme for discriminating n charge levels of a memory cell in which (n-1) comparators and (n-1) voltage references are used in parallel to determine the charge level of the memory cell. Additional decoding logic is required to translate the outputs of the comparators into bits. A total of (2n - 1) different voltage amplitudes are necessary, and have to be implemented on chip. Other multilevel storage memory devices and programming methods have been disclosed in PCT published application WO95/34074, U.S. Pat. No. 5,422,845 and PCT published patent application WO95/34075.
A main disadvantage applying to the memory devices disclosed in the prior art is that they, in functioning, make use of a bit-by-bit program verification procedure. This procedure suffers from trade-offs between accuracy of the stored levels and programming speed. Consequently the programming operation slows down. Moreover, the chip implementation of the verification procedure increases the chip dimensions. Furthermore, the memory devices reported in the prior art employ read-out circuits based on a plurality of comparators and decoding logic which not only increase the complexity of the memory device but also enlarge the chip dimensions.
The prior art memory cells for multi-level charge storage employ programming methods based on either Fowler Nordheim Tunneling (FNT) or Channel Hot Electron (CHE) injection. The prior art multi-level programmming methods utilize a `program verify scheme` comprising the following common steps: duration is applied to the memory cell to be programmed; presented to
REFERENCES:
patent: 4415992 (1983-11-01), Adlhoch
patent: 4532535 (1985-07-01), Gerber et al.
patent: 4558344 (1985-12-01), Perlegos
patent: 4616245 (1986-10-01), Topich et al.
patent: 4649520 (1987-03-01), Eitan
patent: 4670675 (1987-06-01), Donoghue
patent: 4771404 (1988-09-01), Mano et al.
patent: 5043940 (1991-08-01), Harari
patent: 5073513 (1991-12-01), Lee
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5291439 (1994-03-01), Kauffmann et al.
patent: 5298808 (1994-03-01), Terrell et al.
patent: 5418743 (1995-05-01), Tomioka et al.
patent: 5422845 (1995-06-01), Ong
patent: 5583810 (1996-12-01), Van Houdt et al.
patent: 5583811 (1996-12-01), Van Houdt et al.
patent: 5753950 (1998-05-01), Kojima
patent: 5841697 (1998-11-01), Van Houdt et al.
Etiemble et al., "Coneption Avec Regles En Lambda D'une Rom 4-Valuee", Revue de Physique Appliquee, vol. 20, No. 2, pp. 71-75.
Groeseneken Guido
Houdt Jan Van
Maes Herman
Montanari Donato
Le Thong
Nelms David
Siemens Aktiengesellschaft
LandOfFree
Device and method for multi-level charge/storage and reading out does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device and method for multi-level charge/storage and reading out, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device and method for multi-level charge/storage and reading out will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2219275