Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-08-30
2002-09-17
Sherry, Michael J. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S762010
Reexamination Certificate
active
06452415
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates in general to integrated circuits (ICs) fabricated on semiconductor wafers and, more specifically, to devices and methods for isolating a short-circuited IC from other ICs on a semiconductor wafer so that, for example, probe testing may proceed on the other ICs on the wafer despite the presence of the short-circuited IC.
2. State of the Art
As shown in
FIG. 1
, integrated circuits (ICs)
10
are small electronic circuits formed on the surface of a wafer
12
of semiconductor material, such as silicon, in an IC manufacturing process referred to as “fabrication.” Once fabricated, ICs
10
are electronically probed to evaluate a variety of their electronic characteristics. Probing typically involves positioning needle-like probes (not shown) onto bond pads
14
on the surfaces of ICs
10
to test the ICs
10
using various electronic signals supplied through the probes. As described in U.S. Pat. Nos. 5,059,899 and 5,214,657 to Farnworth et al., in some cases, ICs
10
are tested using test probes that contact probe pads
16
positioned on the surface of a semiconductor wafer
12
rather than, or in addition to, contacting bond pads
14
on the ICs
10
.
Sometimes shorts develop in some of the ICs
10
on a semiconductor wafer
12
as a result of fabrication errors. These shorts can interfere with the probe testing described above in a variety of ways. For example, in some instances, a supply voltage V
CC
, provided to ICs
10
on a wafer
12
through probes contacting bond pads
14
on the ICs
10
or probe pads
16
on the wafer
12
, may be shorted to ground through one of the ICs
10
. As a result, over-current protection circuitry, such as a fuse, present in testing equipment that provides the supply voltage V
CC
to the probes, will likely “trip” the equipment off-line, causing a brief but significant delay in the manufacturing of ICs
10
while the equipment is reset. In addition, such a V
CC
-to-ground short in an IC
10
may make the entire wafer
12
untestable until the IC
10
with the short is identified and either repaired or disconnected, which involves a separate manual process that can cause additional delays in the manufacturing process.
In other instances, a test signal V
TEST
supplied to a group of ICs
10
on a semiconductor wafer
12
through a probe pad
16
on the wafer
12
may be distorted for all of the ICs
10
in the group by, for example, a V
TEST
-to-ground or a V
TEST
-to-V
CC
short in one of the ICs
10
in the group. This distortion may interfere with probe testing of all of the ICs
10
in the group, and may require that the IC
10
with the short be manually identified and repaired or disconnected before the ICs
10
in the group can be successfully probe tested.
Therefore, there is a need in the art for a device and method for isolating a short-circuited IC on a semiconductor wafer from other ICs on the wafer. Preferably, such a device and method should isolate a short-circuited IC before the IC interferes with probe testing of other ICs so the probe testing can continue uninterrupted.
SUMMARY OF THE INVENTION
An inventive device for isolating a short-circuited integrated circuit (IC) from other ICs formed on the surface of a semiconductor wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.
Further embodiments of the present invention are directed to an IC including the control and switching circuitry described above, a semiconductor wafer including many of these ICs, and an electronic system, such as a computer system, including at least one of these ICs.
In an inventive method for testing ICs formed on the surface of a semiconductor wafer, control circuitry is provided in the ICs for sensing shorts in the ICs. The ICs are then tested, and if the control circuitry in one of the ICs senses a short, the short-circuiting IC is automatically switchably isolated from the other ICs.
REFERENCES:
patent: 4743841 (1988-05-01), Takeuchi
patent: 4935645 (1990-06-01), Lee
patent: 4967151 (1990-10-01), Barish et al.
patent: 4970454 (1990-11-01), Stambaugh et al.
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5105362 (1992-04-01), Kotani
patent: 5214657 (1993-05-01), Farnworth et al.
patent: 5289113 (1994-02-01), Meaney et al.
patent: 5294883 (1994-03-01), Akiki et al.
patent: 5397984 (1995-03-01), Koshikawa
patent: 5568408 (1996-10-01), Maeda
patent: 5838163 (1998-11-01), Rostoker et al.
patent: 5898700 (1999-04-01), Kim
patent: 5994912 (1999-11-01), Whetsel
Beffa Raymond J.
Cloud Eugene H.
Farnworth Warren M.
Nevill Leland R.
Waller William K.
Micro)n Technology, Inc.
Sherry Michael J.
Tang Minh N.
TraskBritt
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