Coded data generation or conversion – Phase or time of phase change
Reexamination Certificate
2001-10-25
2003-12-09
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Phase or time of phase change
C341S110000, C341S112000, C341S118000, C341S120000, C341S129000, C341S143000, C341S155000, C360S046000, C360S065000, C360S077020, C360S078040, C331S00100A, C331S016000, C331S025000
Reexamination Certificate
active
06661359
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention refers to a device and method for generating synchronous numeric signals.
2. Description of the Related Art
As is known, the use of numeric-type control systems is increasingly widespread in various fields. As compared to traditional purely analog control systems, in fact, numeric control systems are extremely versatile and are, moreover, very often simpler to design, less subject to failure, and less costly. In practice, in numeric control systems a microprocessor, or digital signal processor (DSP), receives, through an analog-to-digital converter, a measured signal correlated to a quantity to be controlled that is present in a system controlled and sampled at a preset control frequency. The measured signal is numerically processed to generate a control signal (having a frequency equal to the control frequency), which is supplied to an actuator for modifying the state of the controlled system and for keeping the quantity to be controlled close to a target value.
For numeric control systems to be efficient, it is, however, necessary to provide accurate analog-to-digital converters that convert with sufficient precision the signals supplied by the sensors and/or transducers that are present. In traditional A-D converters, the above aim is achieved by generating a plurality of reference voltages, the values whereof are normally determined by very precise resistive or capacitive ratios. On the other hand, the fabrication of resistive and capacitive components of controlled value (“matching”) involves the use of sophisticated and costly processing steps to minimize the inevitable process-induced dispersions. In addition, all the resistive or capacitive components used for generating the reference voltages should respond in a homogeneous way to external stresses, for example thermal stresses.
To overcome the problems outlined above, A-D converters of sigma-delta type are in some cases preferred to traditional A-D converters. In fact, sigma-delta A-D converters have a very simple circuit structure and normally require a single reference voltage to be generated: their fabrication thus involves less complex and less costly processing steps and, in addition, sigma-delta converters are less sensitive to process-induced variations.
The use of these converters involves, however, a number of problems. It is, in fact, known that a sigma-delta converter receives an analog signal and outputs a sequence of bits that represent the sign of the variations of the analog signal at each operating cycle of the converter. To reconstruct a sample representing the value of the analog signal at a given instant, it is first of all necessary to oversample the analog signal, feeding the sigma-delta converter with a timing signal having a higher frequency than the control frequency. Then, by through a decimator, it is necessary to filter the bit sequence supplied by the sigma-delta converter and to select filtered samples, eliminating excess samples, so as to obtain a decimated signal having a decimation frequency equal to the required control frequency.
Normally, however, the decimation frequency is only approximately equal to the control frequency in that it is impossible to guarantee that the frequency of the timing signal will be exactly equal to an integer multiple of the sampling frequency. Consequently, it may occur that, in certain control cycles, no sample of the decimated signal will be supplied to the microprocessor, or else that, instead, a more recent sample will overwrite an older sample which has not yet been used by the microprocessor.
For more clarity, a condition with the decimation frequency lower than the control frequency is illustrated in
FIGS. 1
a
-
1
e
, which show: the plot of a timing signal synchronous with the control signal and activating control cycles (
FIG. 1
a
); a sequence of decimation pulses (
FIG. 1
b
); switchings of the decimated signal (
FIG. 1
c
); the latency of the samples of the decimated signal, i.e., the time intervals between each decimation and when the selected sample is made available to the microprocessor (
FIG. 1
d
); and the instants at which a new value of the control signal is supplied (
FIG. 1
e
).
As may be noted, in some control cycles no sample is taken (i.e., no decimation pulses are present); consequently, in the immediately following control cycles, the microprocessor is not able to supply new values of the control signal, and wait cycles with no control action occur.
On the other hand, it is known that the recurrent presence of wait cycles, in which control actions cannot be performed, significantly degrades the performance of the control system. In addition, the phase delay of the decimated signal which is read by the microprocessor and affects the stability of the control system is variable and unpredictable, in so far as the latency of the samples is variable.
Alternatively, it is possible to carry out a frequency conversion before the data generated are read by the microprocessor. In this case, the sequence of samples supplied by the sigma-delta converter is initially filtered with a reconstructing filter to generate a sequence of reconstructed samples, and is then expanded, inserting between two successive samples a first preset integer L of zero samples corresponding to instants comprised in a same sampling interval. The expanded sequence of data is then filtered through a low-pass filter so as to replace the zero samples with interpolated samples. Next, a decimation of the expanded sequence of data is performed, keeping one sample every M samples (M being a second pre-set integer) and eliminating all the others. By choosing the numbers L and M in such a way that the following condition is satisfied:
F
C
=
L
+
1
M
F
s
where F
C
is the control frequency and F
S
is the frequency of the sequence of reconstructed samples, the decimated sequence of data has a frequency equal to the control frequency F
C
and may thus be used to generate the control signal.
However, also the frequency conversion causes a phase delay, and hence adversely affects the stability of the control system. Furthermore, frequency conversion is performed using microprograms (firmware), and this entails both problems of bulk in so far as it is necessary to provide nonvolatile memories, and an increase in the required processing power.
From the above, it is evident that the use of sigma-delta converters that are not properly synchronized involves even serious difficulties. In particular, the stability of the control systems may be impaired.
The aim of the present invention is to overcome the drawbacks of known devices and, in particular, to generate a numeric signal synchronized in frequency and in phase with a reference numeric signal.
SUMMARY OF THE INVENTION
According to one aspect of the present invention there is provided a device for generating synchronous numeric signals, comprising: reference generating means supplying a reference signal and a first timing signal, both having a reference frequency; timed generating means supplying a synchronized signal having said reference frequency; and synchronization means generating a second timing signal having a first controlled frequency correlated to said reference frequency, and phase synchronization pulses having said reference frequency and a preset delay programmable with respect to said first timing signal.
Another aspect of the invention provides a method for generating synchronous numeric signals, comprising the steps of: generating a reference signal and a first timing signal, both having a reference frequency; and generating, from said first timing signal, a second timing signal having a first controlled frequency correlated to said reference frequency, and phase synchronization pulses having said reference frequency and a preset delay programmable with respect to said first timing signal.
For a better understanding of the present invention, a preferred embodiment thereof is now described, purely as a non-limiting example, with refe
Hernden Charles G.
Pasolini Fabio
Carlson David V.
Jorgenson Lisa K.
Nguyen Linh V
STMicroelectronics Inc.
Tokar Michael
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