Device and method for generating read addresses for video memory

Details Device and method for generating read addresses for video memory Device and method for generating read addresses for video memory

1996-07-03

1997-04-29

Brier, Jeffery

Computer graphics processing and selective visual display system

Display driving control circuitry

Physically integral with display elements

G09G 536

Patent

active

056253834

ABSTRACT:
A read address generator for generating read addresses for a read memory wherein input read addresses indicated using an orthogonal coordinate system is converted into equivalent addresses in a polar coordinate system; the polar coordinate system is divided into concentric blocks according to distances from the pole of the polar coordinate system; vectors having sequentially increasing or decreasing angles are set for the concentric block; coordinate values indicated by the vectors are converted into second equivalent coordinate values in the orthogonal coordinate system; and output read addresses are generated by subtracting the second coordinate values from the input read addresses indicated in said orthogonal coordinate system and are supplied to the video memory.

REFERENCES:
patent: 4648049 (1987-03-01), Dines et al.
patent: 5051734 (1991-09-01), Lake, Jr.
patent: 5225824 (1993-07-01), Yamamoto et al.
WPI Abstract Acc No: 93-023134/03 and JP 04 351078 A (NEC) see abstract.

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