Device and method for fabricating double-sided SOI wafer...

Details Device and method for fabricating double-sided SOI wafer... Device and method for fabricating double-sided SOI wafer...

2006-01-04

2009-02-10

Lindsay, Jr., Walter L (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257SE23067, C257SE23092, C257S789000

Reexamination Certificate

active

07489025

ABSTRACT:
A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide which optically connects the chip(s) to the integrated circuit system.

REFERENCES:
patent: 5394490 (1995-02-01), Kato et al.
patent: 5987198 (1999-11-01), Hirota et al.
patent: 6355501 (2002-03-01), Fung et al.
patent: 6548391 (2003-04-01), Ramm et al.
patent: 6607938 (2003-08-01), Kwon et al.
patent: 6645832 (2003-11-01), Kim et al.
patent: 6730541 (2004-05-01), Heinen et al.
patent: 6737297 (2004-05-01), Pogge et al.
patent: 6762076 (2004-07-01), Kim et al.
patent: 6787916 (2004-09-01), Halahan
patent: 2003/0148552 (2003-08-01), Halahan
patent: 2004/0124541 (2004-07-01), Wu et al.
patent: 2004/0155337 (2004-08-01), Strandberg et al.
patent: 1185655 (1998-06-01), None
patent: 1214545 (1999-04-01), None

Affiliated with

Also associated with

Rating

Device and method for fabricating double-sided SOI wafer... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Device and method for fabricating double-sided SOI wafer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device and method for fabricating double-sided SOI wafer... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4140757