Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-10-06
2001-08-28
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S714000, C438S723000, C438S724000
Reexamination Certificate
active
06281132
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to an improved dry etch method of use in the formation of nitride spacers.
2. Description of the Related Art
Fabrication of a metal oxide semiconductor field-effect transistor (MOSFET) device is well known. MOSFETs are generally manufactured by placing an undoped polycrystalline silicon (“polysilicon”) material over a relatively thin layer of silicon dioxide (“oxide”). The polysilicon material and the oxide are then patterned to form a gate conductor arranged upon a gate oxide with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species.
Operating transistors which have heavily doped source/drain regions arranged directly adjacent to the gate conductor often experience a problem known as hot carrier injection (“HCI”). HCI is a phenomena by which the kinetic energy of the charged carriers (holes or electrons) is increased as they are accelerated through large potential gradients, causing the charged carriers to become injected into and trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field (“Em”), occurs near the drain during saturated operation. Because of carrier entrapment within the gate oxide, a net negative charge density forms in the gate oxide. The trapped charge can accumulate with time, resulting in a positive threshold shift in a NMOS transistor or a negative threshold shift in a PMOS transistor.
To overcome problems of sub-threshold current and threshold shift resulting from HCI, an alternative drain structure known as the lightly doped drain (“LDD”) is commonly used. The purpose of the LDD is to absorb some of the potential into the drain and thus reduce Em. A conventional LDD structure is one in which a light concentration of dopant is self-aligned to the gate conductor followed by a heavier concentration of dopant self-aligned to the gate conductor on which two sidewall spacers have been formed. The purpose of the first implant dose is to produce a lightly doped section within the active area (hereinafter “junction”) at the gate edge near the channel. The second implant dose is used to form a heavily doped source/drain region within the junction laterally outside the LDD area. Because the second implant dose is spaced from the channel by the spacers, the lateral thickness of the spacers dictates the length of the LDD and source/drain regions.
The spacers are typically formed by first chemical vapor depositing (“CVD”) an oxide layer over the gate conductor. The oxide layer is then patterned to form spacers on the sidewall of the gate conductor. While oxide spacers are commonly used in MOSFETs, these spacers do have drawbacks. For example, the boron used to form junctions in PMOSFET devices may migrate from the silicon substrate into oxide spacers. This boron up-diffusion can undesirably reduce the dopant density in the underlying junctions. In addition, metal deposited over oxide spacers during the process of salicide formation may react with silicon in the spacers to form a silicide that bridges across the separation between the source/drain regions and the gate conductor provided by the spacers. This phenomenon, referred to as “silicide shorting”, can cause the gate to become shorted to the source/drain regions.
The aforementioned problems of oxide spacers can be mitigated by the use of spacers composed of silicon nitride (“nitride”). Nitride is a fairly stable material and is nearly impervious to diffusion, making it an excellent barrier material. Because of this property, dopants such as the boron in the junctions of PMOSFET devices are substantially prevented from up-diffusing into nitride spacers. Furthermore, the diffusion length of the silicon within nitride spacers is fairly short and therefore does not readily react with the metal deposited over the spacers during the salicidation process. As a result, the likelihood of silicide shorting occurring is greatly reduced.
Two methods commonly used to deposit nitride layers are low pressure chemical vapor deposition (“LPCVD”) and plasma enhanced chemical vapor deposition (“PECVD”). LPCVD deposition of nitride commonly involves the formation of nitride from a reaction between dichlorosilane and ammonia at relatively low pressures, but at high temperatures (e.g., 700-800° C.). In PECVD deposition of nitride, silane is usually reacted with nitrogen and/or ammonia at relatively low temperatures (200-400° C.) in a plasma. In general, spacers formed from PECVD nitride layers are softer and less stoichiometric than spacers arising from LPCVD nitride layers.
Even with the potential problems of nitride spacers, oxide spacers are still used. Consequently, a fab must usually have processes in place capable of forming nitride and oxide spacers. The differences in etch chemistries of oxide and nitride, however, often necessitate a dedicated etch tool for each species. Unfortunately, wafers often contain layers of oxide and nitride that must be etched in succession. Having to transfer the wafer from one etch system to another adds time to the fabrication process and reduces throughput. Moreover, an undesirable risk of contamination is created when the wafer must be transferred between reaction chambers. It would be desirable, therefore, to create a process that would allow nitride and oxide layers to be etched by a single tool.
Regardless of the type of spacers to be formed, the layer from which the spacers are formed is preferably deposited conformally. As a result of this conformal deposition, the layer is often thicker at the edges of the gate-to-junction steps then on flat (horizontal) areas. An anisotropic etch process will thus clear the layer from the flat areas while leaving spacers on the sidewalls of the gate electrode. Because of the ability of dry etch processes to etch anisotropically (in comparison to wet etch processes, which etch isotropically), dry etching is typically used in spacer formation.
There are three types of dry etch processes: those that have a physical basis (e.g., ion beam milling), those that have a chemical basis (e.g., plasma etching), and those that combine both physical and chemical mechanisms (e.g., reactive ion etching). Primarily physical dry etch methods may not exhibit sufficient selectivity to both masking materials and the underlying substrate, while primarily chemical processes typically etch isotropically. Consequently, ion-assisted etching processes that combine the two mechanisms are often preferred in spacer fabrication.
Ion assisted etching can be carried out in a variety of types of commercial dry etch systems. One commonly used configuration is the parallel electrode reactor system. These systems typically have a diode configuration with two parallel, circular electrodes spaced by a gap. One of the electrodes is connected to a radio frequency (“RF”) power supply, and the other is grounded. The wafer is placed on the to-be-powered electrode. A pump is used to adjust the pressure within the reaction chamber to the desired level, and etchant gases are introduced into the reaction chamber. By applying power to an electrode, a plasma may be created within the chamber. Because the wafer is placed on the powered electrode, energized ions from the plasma may bombard the wafer. The combination of physical and chemical processes allows for etching that is both anisotropic and selective. The degree of anisotropy and selectivity, as well as other factors such as the etch rate, are determined by a variety of parameters. These parameters include: the quantity and frequency of the power supplied, the gap between the electrodes, the type and flow rate of etchant gas into the reaction chamber, and the pressure within the reaction chamber.
The values of the above-listed parameters selected for a particular etching process can have a significant impact on the properties of the final integrated
Gardner Mark I.
May Charles E.
Nguyen Thien T.
Advanced Micro Devices , Inc.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Umez-Eronini Lynette T.
Utech Benjamin L.
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