Excavating
Patent
1997-06-03
1999-06-22
Grant, William
Excavating
371 376, 3647461, H03M 1300
Patent
active
059149698
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to device and method for error correcting coding, as well as device and method for error correcting decoding. In particular, the invention relates to device and method for error correcting coding for encoding error correcting codes for correcting errors in digital data during the recording or reproduction, or transmission or reception of digital data executed by digital recording equipment or digital communication equipment similar devices, and also relates to device and method for error correcting decoding for decoding error correcting codes.
BACKGROUND ART
In recent years, with the development of digital recording equipment and digital communication equipment, an important issue has been raised on how errors of digital data are reduced during the recording or reproduction, or transmission or reception of digital data. Thus, for correction of errors of digital data, error correcting codes are used in various types of equipments that treat digital data. The Reed-Solomon code is also one type of such error correcting codes, and is used primarily in, for example, digital recording devices such as PD drive units utilizing phase change.
The Reed-Solomon code is a multi-element cyclic Hamming code in which the code word consists of elements of a Galois field GF(2.sup.N) whose number of elements is 2.sup.N, and in which if .alpha. is the primitive element of GF(2.sup.N), then the generator polynomial can be expressed by the following equation:
Hereinafter, computational operations including the Equation (1) will be all executed on the Galois field GF(2.sup.N). Also, d denotes the minimum inter-code distance.
Code words in the Reed-Solomon code are generated as follows:
If an information word vector I is expressed as follows: .sub.k-2 .multidot.X+i.sub.k-1 ( 3) respectively, and are associated with vector representations of elements on the Galois field GF(2.sup.N) by handling N bits as one set with respect to bit data that are the source of information.
Then, a code polynomial A(X) can be calculated from the information polynomial I(X) and the generator polynomial G(X) by using the following equation:
However, the code obtained would not be a systematic code. Therefore, a code word is created as follows.
First of all, the information polynomial I(X) is multiplied by X.sup.n-k, and the result is divided by G(X). If the quotient is Q(X) and the remainder is R(X), then the following expression can be given:
The A(X) calculated by the Equation (7) is divisible by the generator polynomial G(X), thus resulting in a code polynomial. If the code polynomial R(X) is expressed as follows: +r.sub.n-k-2 .multidot.X+r.sub.n-k-1 ( 8) expressed as follows: ##EQU1##
The code word represented by the code polynomial of the Equation (9) can be represented in vector representation as follows: r.sub.n-k-1) (10) information word vector I as it is, proving that it is a systematic code. In this case, the code word vector A is a (n, k) systematic code. Upon creating a code word, a vector R to be added to the information word vector, that is,
The code generated in this way as shown above is written as a Reed-Solomon code RS (n, k, d=n-k+1).
FIG. 12 shows an example of the device for error correcting coding according to the prior art using the Reed-Solomon code. This circuit performs the division of polynomials having coefficients of Galois field GF(2.sup.N) Referring to FIG. 12, the device for error correcting coding comprises: k.sub.1 on the Galois field; the 8-bit latches 183 to 194 upon a reset.
In this device for error correcting coding, input data is inputted to a first input terminal of the EXCLUSIVE-OR computing unit 206. The output data from the output terminal of the EXCLUSIVE-OR computing unit 206 is inputted to the 8-bit latch 183 via the coefficient multiplier 171, while the output data therefrom is inputted to the EXCLUSIVE-OR computing units 195 to 205 via the coefficient multipliers 172 to 182, respectively. Further, the 8-bit latches 183 to 194 and the EXCLUSIVE-OR computing
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Kuang Y. Liu, "Architecture for VLSI Design of Reed-Solomon Encoders", IEEE Transactions on Computers, vol. C-31, No. 2, pp. 170-175, Feb. 1982.
Yabuno Hiroyuki
Yumiba Takashi
Grant William
Marc McDieunel
Matsushita Electric - Industrial Co., Ltd.
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