Device and method for error and sync detection

Details Device and method for error and sync detection Device and method for error and sync detection

2006-11-21

2006-11-21

To, Doris H. (Department: 2616)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C714S798000, C714S799000, C714S746000

Reexamination Certificate

active

07139289

ABSTRACT:
In an error and sync detection circuit, 7-bit byte data is rearranged by a data rearrangement block into 8-bit byte data where 1 byte is comprised of 8 bits. Thereafter, the 8-bit byte data is consistently used throughout the process, and each of such byte data is stored in a data storage block, which is a RAM. In a parity check block, a sync detection operation and a parity check operation are performed on the byte data from the data rearrangement block and the byte data from the data storage block, which has been delayed by 1496 clocks. Thus, the byte-to-byte conversion process eliminates the need for a parallel-to-serial conversion circuit and a serial-to-parallel conversion circuit. Use of a RAM for storing the byte data eliminates the need for a 1496-stage delay element.

REFERENCES:
patent: 5646941 (1997-07-01), Nishimura et al.
patent: 5703887 (1997-12-01), Heegard et al.
patent: 2001/0005385 (2001-06-01), Ichiguchi et al.
patent: 2002/0004925 (2002-01-01), Kodama et al.
patent: 2003/0014763 (2003-01-01), Chappell et al.
patent: 8-179924 (1996-07-01), None
patent: 11-252062 (1999-09-01), None
“Digital Multi-Programme Systems for Television, Sound and Data Services for Cable Distribution” ITU-T Recommendation J.83, pp. 1-60, Apr. 1997.

Affiliated with

Also associated with

Rating

Device and method for error and sync detection does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Device and method for error and sync detection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device and method for error and sync detection will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3655921