Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
2002-06-17
2004-07-27
Phan, Man (Department: 2665)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S503000, C370S515000, C370S465000, C375S367000, C375S371000
Reexamination Certificate
active
06768734
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a device and a method for equalizing data delays in a multiplicity of serial input data streams switched, for example, by a switching network in a telecommunication switching system.
In particular, the present invention relates to a device and a method for equalizing data delays used, for example, in Type D of the Siemens EWSD switching system. This novel switching system is especially characterized by a compressed data stream in which, for example, 16 conventional line trunk groups are combined to form one data stream. One frame in a time-division multiplex system compressed in this manner preferably exhibits (in addition to 2×128 test channels) 16×128 payload channels with, in each case, 80 kbit/s. However, since different delays can occur for the 16 combined line trunk groups, a data frame having different lengths is obtained in the compressed data stream which is essentially composed of the data streams of the 16 line trunk groups. More precisely, a fluctuation internal to the frame, which is essentially caused by delay differences of the line trunk groups, occurs for the associated data frames in the compressed data stream.
If, in addition, a multiplicity of such compression units combine, in each case, 16 line trunk groups, different start and end points are also obtained again for the respective data frames between the compressed data streams.
The present invention is, therefore, directed toward creating a device and a method for equalizing data delays in a multiplicity of serially compressed input data streams, wherein a multiplicity of mutually synchronous data streams are output simultaneously and in phase at the output.
SUMMARY OF THE INVENTION
It is particularly by using a multiplicity of data word synchronization units for synchronizing the multiplicity of input data streams at a data word level into a multiplicity of synchronized parallel input data streams, the synchronizing at data word level representing an insertion or discarding of at least one predetermined code word into the multiplicity of input data streams, that a device and a method for equalizing data delays, in which the data streams output can be output absolutely synchronously and simultaneously without phase shifts are obtained in a relatively simple manner.
A multiplicity of serial/parallel converters are preferably used for converting a compressed serial input data stream into a parallel data stream of the multiplicity of input data streams which allows a data rate of the data stream to be significantly reduced. Before the serial/parallel conversion, the phases of the input data streams are aligned to the internal 184 MHz clock with the aid of so-called phase aligners. Phase aligners are analog circuits which are able to detect a change from 0 to 1, or from 1 to 0 and can then allocate the signal to the preferred phase.
The multiplicity of data word synchronization units, in each case, preferably, consist of variable serial storage units and an associated control unit, as a result of which the serial/parallel converted input data stream can be selectively processed further for different times. The buffers used are a multiplicity of storage devices which can be simultaneously read out via parallel/serial converters which results in a multiplicity of serial data streams at the output which are output exactly synchronously and with identical data frame length.
Additional features and advantages of the present invention are described in, and will be apparent from, the following Detailed Description of the Invention and the Figures.
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Bell Boyd & Lloyd LLC
Phan Man
Siemens Aktiengesellschaft
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