Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-12-13
2002-06-04
Hjerpe, Richard (Department: 2774)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S067000, C345S068000, C345S069000, C345S211000
Reexamination Certificate
active
06400344
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a surface discharge type plasma display panel and more particularly to a technique for driving an address electrode thereof.
DISCUSSION OF THE BACKGROUND
FIG. 56
is a circuit diagram showing a state of address electrode driving of a surface discharge type plasma display panel. Scan electrodes X and Y
k
intersect an address electrode A
j
for one display cell C
jk
of the surface discharge type plasma display panel (j, k=1, 2 . . . ).
In such a surface discharge type plasma display panel, there has conventionally been proposed a technique that a negative pulse is not given to the scan electrode Y
k
but a great positive pulse is given to the address electrode A
j
when performing a so-called “priming discharge” in which a history in the display cell C
jk
is erased and a space charge is left. The reason is that a positive pulse can be generated more simply and easily than a negative pulse.
A high voltage generating circuit AD
1
and an address drive circuit AD
2
for switching an output of the high voltage generating circuit AD
1
or a ground potential and for outputting the same to the address electrode A
j
are provided corresponding to the address electrode A
j
. The address drive circuit AD
2
comprises switches SW
3
and SW
4
which are connected in series between the output of the high voltage generating circuit AD
1
and the ground potential, and diodes D
3
and D
4
connected in parallel with the switches SW
3
and SW
4
respectively.
The scan electrode X is provided with a drive circuit SD
3
for generating a voltage to be applied to the scan electrode X. Furthermore, a scanning drive circuit SD
1
and a switch circuit SD
2
for switching an output of the scanning drive circuit SD
1
or a ground potential and for outputting the same to each scan electrode Y
k
are provided corresponding to the scan electrode Y
k
.
Such a structure has been described in Japanese Patent Laid-open No. P07-160218A, for example, in which the high voltage generating circuit AD
1
and the address drive circuit AD
2
are indicated as the reference numerals
233
a
and
233
bj,
respectively.
To the address electrode A
j
are respectively applied a voltage Vaw for a priming discharge for write preparation (“a reset period” described in the Japanese Patent Laid-open No. P07-160218A), a voltage Va for a write discharge (“an address period” described in the Japanese Patent Laid-open No. P07-160218A) and a voltage Vaw for a sustain discharge period (“a sustain discharge period” described in the Japanese Patent Laid-open No. P07-160218A).
For the reset period and the sustain discharge period, a switch SW
2
of the high voltage generating circuit AD
1
is turned off and a switch SW
1
thereof is turned on so that a voltage Vas supported by a Zener diode is added to the voltage Va supplied from a power source and a voltage Vaw(=Va+Vas) is output from the high voltage generating circuit AD
1
. Then, the switches SW
4
and SW
3
of the address drive circuit AD
2
for all the address electrodes A
j
are turned off and on, respectively. Consequently, the voltage Vaw is supplied to all the address electrodes A
j
.
However, a rated voltage of an IC constituting the high voltage generating circuit AD
1
and the address drive circuit AD
2
should be set equal to or higher than a maximum value of a voltage to be used in the above-mentioned procedure. For this reason, the rated voltage of the IC should be equal to or higher than the voltage Vaw(=Va+Vas) which is higher than the voltage Va required for the write discharge and is required for the sustain discharge period.
More specifically, an IC having a high breakdown voltage is required to output a high voltage for the reset period and the sustain discharge period. As a result, a cost is increased. Moreover, since the voltages to be output for the reset period and the sustain discharge period are also influenced by the performance of the IC, a value thereof is limited.
In a conventional method, furthermore, in the case where the switch SW
3
on a high arm of the address drive circuit AD
2
is turned on to output “H” for the write discharge period, a current sometimes flows into the address electrode A
j
in a suction direction by the output of the scan electrodes X and Y
k
.
FIG. 57
is a circuit diagram showing, in detail, a structure of the address drive circuit AD
2
illustrated in
FIG. 56
, in which the display cell C
jk
is replaced by an electrically equivalent circuit. There exists an equivalent capacitor CP between the scan electrode Y
k
and the address electrode A
j
. Similarly, the equivalent capacitors exist between the scan electrode X and the address electrode A
j
and between the scan electrode X and the scan electrode Y
k
. The switches SW
3
and SW
4
of the address drive circuit AD
2
are implemented by MOS transistors T
1
and T
2
, respectively.
The address drive circuit AD
2
gives “H” to the address electrode A
j
so that the equivalent capacitor CP is charged. With such charging kept, switches SW
5
and SW
6
are turned on and off in the switch circuit SD
2
for the sustain discharge period, respectively. When the voltage of the scan electrode Y
k
is changed to “H”, the electric potential of the address electrode A
j
tries to perform step-up by the equivalent capacitor CP. At this time, the diode D
3
of the address drive circuit AD
2
causes a current to flow to the power source side for supplying the electric potential Va, thereby preventing the step-up of the voltage.
In this case, if the MOS, transistors T
1
and T
2
constituting the address drive circuit AD
2
are not formed by using a dielectric isolating method but a self-isolating technique, a parasitic transistor is generated. Consequently, the following problem arises.
FIG. 58
is a sectional view showing structures of the MOS transistors T
1
and T
2
formed by using the self-isolating technique. A PNP transistor T
3
is parasitic on the PMOS transistor T
1
, and a base current of the parasitic transistor flows with a rise in the electric potential of the address electrode A
j
. Consequently, a short-circuit current
12
flows from the power source for supplying the electric potential Va to a ground through the transistors T
1
and T
3
. Therefore, there is a possibility that the address drive circuit AD
2
might be subjected to a thermal breakdown.
SUMMARY OF THE INVENTION
A first aspect of an address electrode driving apparatus for driving an address electrode for a surface discharge type plasma display panel having a plurality of scan electrodes, a plurality of address electrodes which are orthogonal to the scan electrodes, and a display cell formed on each of intersecting points of the scan electrodes and the address electrodes, in accordance with the present invention, is that the apparatus comprises a plurality of drive circuits including a first number of output stages, each output stage having an output terminal provided corresponding to each of the address electrodes and connected thereto, and a first input terminal and a second input terminal, one of which is selectively connected to the output terminal, a first power control circuit for supplying, to the second input terminal, one of a reference potential and a first electric potential which is higher than the reference potential, and a second power control circuit for supplying, to the first input terminal, a second electric potential which is lower than the first electric potential and is higher than the reference potential or connecting the first input terminal to the second input terminal.
A second aspect of the address electrode driving apparatus in accordance with the present invention is that the apparatus of the first aspect further comprises a control circuit for outputting drive data which serves to set the output terminal of the drive circuit to be connected to the first input terminal or the second input terminal, and a plurality of transmitting circuits provided corresponding to each of the address electrodes for tran
Hashimoto Takashi
Iwata Akihiko
Nakanishi Takahito
Someya Jun
Tsunoda Yoshikazu
Dinh Duc Q
Hjerpe Richard
Mitsubishi Denki & Kabushiki Kaisha
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