Device and method for digitally generating equidistant...

Details Device and method for digitally generating equidistant... Device and method for digitally generating equidistant...

2005-04-26

2005-04-26

Tran, Khai (Department: 2637)

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

C375S354000

Reexamination Certificate

active

06885717

ABSTRACT:
Uniform distribution of a correction determined by a PLL over the subordinate clock signals is undertaken by dividing a phase-regulated value by the number of subordinate clock signals. Division by way of successive addition is performed such that time conflicts with subordinate clock signals generated in real time are successfully avoided despite the required time duration of such a division. The synchronicity can be further raised by also uniformly distributing a division remainder. A particularly effective implementation of this division employs subsequent rounding for real time use.

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patent: 6154508 (2000-11-01), Ott
patent: 6163185 (2000-12-01), Deluigi et al.
patent: 6304623 (2001-10-01), Richards et al.
patent: 6603830 (2003-08-01), Finsterbusch et al.
patent: 19932635 (2000-08-01), None

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