Device and method for defect handling in semi-conductor memory

Details Device and method for defect handling in semi-conductor memory Device and method for defect handling in semi-conductor memory

1989-10-17

1993-04-06

Beausoliel, Robert W.

Excavating

371 101, 371 102, 371 111, 3642453, 3642853, G11C 2900

Patent

active

052009599

ABSTRACT:
A solid-state memory array such as an electrically erasable programmable read only memory (EEprom) or Flash EEprom array is used to store sequential data in a prescribed order. The memory includes a first information list containing addresses and defect types of previously detected defects. The defects are listed in the same prescribed order as that of the data. Only a simple controller is required to reference the information list so that writing or reading of the data will skip over the defective locations in the memory. New defects may be detected during writing by failure in verification, and those new defects will also be skipped. The memory also includes a second information list maintained by the controller. As data is written to the memory, addresses of file-markers and defects detected by write failure are entered into the list in the same prescribed order. This second list is referenced with the first list by the controller in subsequent reading to skip over both the previously and the newly detected defects.

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