Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
1998-10-30
2001-09-25
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S211000, C327S034000, C327S379000
Reexamination Certificate
active
06294939
ABSTRACT:
BACKGROUND OF THE INVENTION
Semiconductor memories, such as random access memories (RAMs) and read-only memories (ROMs), are typically designed to operate in response to input signals in either a synchronous (clocked) or an asynchronous (unclocked) manner. One type of integrated circuit which operates primarily on asynchronous signals is a static random-access memory (SRAM). An SRAM device is designed to receive data values at data input terminals, and to statically provide the data values to memory cells corresponding to the value of the address applied to the SRAM, without relying on a clock signal indicating that the value at its data input terminals is valid.
Many modern SRAMs now include edge transition detection (ETD) circuits and other timing and control circuits that provide the SRAM device with performance benefits of internal dynamic operation. An ETD circuit detects transitions within the device and generates internal signals or “pulses” responsive to detecting such transitions. The internally-generated ETD pulses are employed to initialize the SRAM for commencement of a memory read or write cycle.
For example, the use of an ETD circuit allows the SRAM circuit to perform certain internal operations, such as precharging bit lines or deselecting sense amplifiers, after detection of an input signal transition. Upon presentation of new set of data to the SRAM, the transitions at the data input terminal cause the ETD circuit to enable the necessary functions of the SRAM in order to write the new data values into the addressed memory cells. An example of an ETD circuit used in SRAMs is described in U.S. Pat. No. 5,124,584, issued on Jun. 23, 1993, assigned to SGS-Thomson Microelectronics and herein incorporated by reference.
Conventional ETD circuitry is not without its shortcomings. For instance, an ETD pulse generated by the ETD circuitry which is utilized to initialize an SRAM device may possess a pulsewidth which is drastically reduced and in some cases eliminated due to input glitches appearing on the data input bus. In addition, ETD circuitry is typically separate and distinct from data input buffer circuitry, thereby increasing silicon layout overhead.
Noise or other interference may appear on an input data bus coupled to an SRAM device which may unexpectantly place the input data bus in an undesirable logic state for a temporary period of time. A noise glitch appearing on an input data bus of a conventional SRAM device may propagate therein and cause the wrong data values to be stored in the SRAM device.
Accordingly, there is a need for a data input buffer device and method for an SRAM for preventing noise appearing on a data input bus from adversely effective data storage and for generating edge transition detection signals with little overhead.
SUMMARY OF THE INVENTION
The present invention overcomes shortcomings associated with asynchronous devices and satisfies a need for an input buffer circuit which substantially eliminates the adverse effects of noise and efficiently generates ETD signals for initializing an SRAM or other asynchronous device.
According to the present invention, there is provided a data input buffer device and method for an asynchronous device, such as an SRAM. The data input buffer device preferably receives an input data bus and generates a logic true or logic complement output signal representative thereof for use by circuitry to which the data input buffer device is coupled, such as control and I/O circuitry for the SRAM device. In order to prevent noise appearing on an input data signal from undesirably overwriting data being stored in a memory cell, the data input buffer circuit preferably includes timing circuitry which filters out noise glitches appearing on the data input bus having a relatively narrow pulsewidth and generates a data output signal having rising and falling edge transitions which occur a predetermined period of time following an edge transition appearing on the data input signal. The timing circuitry preferably includes dual circuit paths wherein a first circuit path generates a first delayed timing signal responsive to a falling edge transition appearing on the data input signal, and a second circuit path generates a second delay timing signal responsive to a rising edge transition appearing thereon. The first and second delayed timing signals trigger a falling edge transition and a rising edge transition on the data output signal, respectively, such that the delay to a rising edge transition appearing on the data output signed is substantially equal to the delay to a falling edge transition thereon, relative to a transition on the data input signal.
The above-mentioned timing circuitry of the data input buffer device is efficiently utilized to additionally detect an edge transition appearing on the data input signal and generate an edge transition detection pulse to initialize the SRAM device for preparation of a new memory cycle, such as a memory read or write operation. By generating the edge transition detection pulse from the timing circuitry that generates the data output signal representation of the input data signal, a relatively sizeable amount of silicon space is saved.
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Cunningham Terry D.
Galanthay Theodore E.
Jorgenson Lisa K.
STMicroelectronics Inc.
Szuwalski Andre
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