Image analysis – Image transformation or preprocessing – Mapping 2-d image onto a 3-d surface
Reexamination Certificate
1999-01-13
2002-09-03
Mehta, Bhavesh (Department: 2721)
Image analysis
Image transformation or preprocessing
Mapping 2-d image onto a 3-d surface
C382S154000, C345S419000, C356S012000, C348S042000
Reexamination Certificate
active
06445833
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an apparatus and method for converting two-dimensional images into three-dimensional images.
2. Related Art
[1] There has been known a method for converting 2D images into 3D images, which method utilizes field memories for generating an image signal (hereinafter referred to as “delayed image signal”) time-delayed relative to an original 2D image signal so as to output either one of the original 2D image signal and the delayed image signal as a left-eye image signal and the other as a right-eye image signal. Unfortunately, however, this method has a disadvantage of high costs because the field memories are necessary for generating the image signal time-delayed relative to the original 2D image signal. In addition, this method is adapted to convert only 2D motion images into 3D motion images.
It is, therefore, an object of the invention to provide an apparatus and method for converting the 2D images into the 3D images, which apparatus and method negate the need for the field memories for generating the image signal time-delayed relative to the original 2D image signal, thereby accomplishing the cost reduction.
It is another object of the invention to provide an apparatus and method for converting the 2D images into the 3D images, which apparatus and method are adapted to produce stereoscopic images even from the original 2D image signal representing still images.
[2] There has already been developed an apparatus for providing a stereoscopic image by committing a signal to display on a 3D display unit, the signal representing a 3D image composed of a left-eye image and a right-eye image having parallax therebetween. Furthermore, an apparatus for generating a 3D image signal from a 2D image signal has already been developed.
However, an apparatus has yet to be developed which is adapted to perform a real-time processing on the 3D image signal for adjustment of a stereoscopic effect of the 3D images produced from the 3D image signal.
It is, therefore, an object of the invention to provide an apparatus and method for performing the real-time processing on the 3D image signal for adjustment of the stereoscopic effect of the 3D images produced from the 3D image signal.
[3] There has been known a 2D/3D image converter which generates, from a 2D image, a first image signal used as a reference and a second image signal time-delayed relative to the first image signal and outputs either one of these image signals as the left-eye image signal and the other as the right-eye image signal thereby converting the 2D image into the 3D image.
As to the first image signal, the original 2D image signal is used as it is. A delay value of the second image signal relative to the first image signal depends upon a motion speed of an image represented the 2D image signal. The second image signal is generated in the following manner.
More specifically, a predetermined number of fields of the 2D image signal inputted in the 2D/3D image converter, which precede the current field, are stored in a plurality of field memories on a field-by-field basis. Then, out of the 2D image signals stored in the respective field memories, read out is a 2D image signal having a delay value determined based on the motion speed of the image represented by the 2D image signal. The 2D image signal read out from the field memory is the second image signal. The left-eye and right-eye image signals thus obtained are each changed in rate to twice the normal rate in order to prevent the occurrence of flickers when the left-eye and right-eye images are viewed through a time division shutter glasses.
FIG. 55
diagrammatically illustrates a construction of a prior-art 2D/3D image converter for generating a double-speed 3D image signal from the 2D image signal.
The 2D/3D image converter includes an integrated circuit (LSI)
1100
for converting the 2D image signal into the 3D image signal, a plurality of delay field memories
1200
connected to the integrated circuit
1100
, and a doubling circuit
1300
for doubling frequencies of the left-eye and right-eye image signals outputted from the integrated circuit
1100
.
FIG. 55
shows only components of the integrated circuit
1100
that are involved in the writing of data to and the reading of data from the delay field memories
1200
. More specifically, the figure shows the components of the integrated circuit
1100
, which include a write data path
1101
, a write timing generating section
1102
, a read data path
1103
and a read timing generating section
1104
. Besides these components, the integrated circuit
1100
includes a motion vector sensing section, an interface connected to a CPU, and the like.
The write timing generating section
1102
and the read timing generating section
1104
are each supplied with a reference clock signal CLK generated based on a horizontal synchronizing signal HSYNC of the 2D image signal, a vertical synchronizing signal VSYNC of the 2D image signal, and a horizontal synchronizing signal HD generated based on the horizontal synchronizing signal Hsync as timed to the reference clock signal CLK. A frequency f
CLK
of the reference clock signal CLK is given by the following equation (1) with f
H
denoting a frequency of the horizontal synchronizing signal HD:
f
CLK
=910f
H
(1)
The integrated circuit (LSI)
1100
is supplied with a luminance signal (Y signal) and color difference signals (R-Y and B-Y signals) which three signals compose the 2D image signal. The integrated circuit
1100
outputs the right-eye and left-eye image signals having a relative time difference therebetween. The right-eye image signal is composed of a right-eye luminance signal Y(R) and right-eye color difference signals R-Y(R) and B-Y(R) whereas the left-eye image signal is composed of a left-eye luminance signal Y(L) and color difference signals R-Y(L) and B-Y(L).
Either one of the right-eye and left-eye image signals is generated from a signal of the 2D image signal inputted in the integrated circuit
1100
, which signal is sent to the read data path
1103
via the write data path
1101
. The other of the right-eye and left-eye image signals is generated from a signal of the 2D image signal inputted in the integrated circuit
1100
, which signal is sent to the read data path
1103
via the write data path
1101
and the delay field memory
1200
.
The Y, R-Y and B-Y signals inputted in the write data path
1101
are written to the field memories
1200
based on the reference signal CLK. Specifically, a clock frequency for writing to the delay field memories
1200
is equal to the frequency f
CLK
of the reference clock signal CLK.
The signals stored in the field memories
1200
are read out based on the reference clock signal CLK. That is, a clock frequency for reading from the delay field a memories
1200
is also equal to the frequency f
CLK
of the reference clock signal CLK.
Accordingly, the right-eye luminance signal Y(R) the right-eye color difference signals R-Y (R) and B-Y (R) the left-eye luminance signal Y (L), and the left-eye color difference signals R-Y (L) and B-Y (L), which are outputted from the integrated circuit
1100
, each have the same horizontal and vertical frequencies with the horizontal and vertical frequencies of the 2D image signals.
The doubling circuit
1300
includes double-speed field memories
1301
-
1306
for respectively storing the right-eye luminance signal Y (R), the right-eye color difference signals R-Y (R) and B-Y (R), the left-eye luminance signal Y (L), and the left-eye color difference signals R-Y (L) and B-Y (L), which are outputted from the integrated circuit
1100
; a double-speed field-memory write timing generating circuit
1307
for controlling the writing of data to these double-speed field memories
1301
-
1306
, and a double-speed field-memory read timing generating circuit
1308
for controlling the reading of data from these double-speed field memories
1301
-
1306
.
When the righ
Ihara Kanji
Maenaka Akihiro
Mori Yukio
Murata Haruhiko
Okada Seiji
Arent Fox Kintner & Plotkin & Kahn, PLLC
Kassa Yosef
Mehta Bhavesh
Sanyo Electric Co. Ltd
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