Device and method for converting analog signal to digital...

Coded data generation or conversion – Analog to or from digital conversion – Multiplex

Utility Patent

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Details

C341S158000

Utility Patent

active

06169504

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analog-to-digital (A/D) converter, and more particularly, to a device and method for converting an analog signal into a digital signal using an interleaving sampling method.
2. Description of the Conventional Art
A feedback-type A/D converter and a parallel/flash A/D converter are two main types of a conventional A/D converter. These types of the conventional A/D converter are discussed on pages 747-753 of
Microelectronic Circuits,
3rd edition, 1990, by Sedra and Smith, and will be described below.
As shown in
FIG. 1
, the conventional feedback-type A/D converter includes a comparator
11
, a counter
12
, and a digital-to-analog (D/A) converter
13
. The comparator
11
has a positive terminal (+) for receiving an external analog signal V
1
and a negative terminal (−) for receiving a reference voltage V
R
. The comparator
11
compares the reference voltage V
R
with the analog signal V
1
, and outputs the result to the counter
12
. The counter
12
counts up or down the signal output from the comparator
11
according to a clock signal input thereto, and outputs an N-bit digital signal to an external source and the D/A converter
13
based on the count. The D/A converter
13
converts the N-bit digital signal output from the counter
12
into an analog signal, and outputs the analog signal to the comparator
11
as the reference voltage V
R
.
Referring to
FIG. 1
, an operation of the conventional feedback-type A/D converter will be described. As shown therein, the comparator
11
compares the reference voltage signal V
R
output from the D/A converter
13
with the analog signal V
1
input externally, and outputs the resultant signal to the counter
12
. The comparator
11
outputs a positive-valued signal when the analog signal V
1
is positive, and a negative-valued signal when the analog signal V
1
is negative. For the initial comparison, the reference voltage signal V
R
output from the D/A converter
13
is set to zero (“0”). The counter
12
receives the signal output from the comparator
11
. The counter
12
performs up-counting when the signal output from the comparator
11
is positive, and down-counting when the signal is negative. The counting operations of the counter
12
are controlled by a clock signal output from an external clock generator (not shown). Then the counter
12
generates an N-bit digital signal according to the count results. The N-bit digital signal is output to an external device and to the D/A converter
13
. The D/A converter
13
converts the N-bit digital signal into an analog signal which is input to the comparator
11
. The comparator
11
treats this signal as the reference voltage signal V
R
, and compares the signal V
R
with the analog signal V
1
input thereto.
The above-described operation is repeatedly performed, and the counter
12
outputs the digital signals (bit
1
to bit N) until the output of the comparator
11
has a value of zero (“0”).
FIG. 2
shows an exemplary circuit of a conventional parallel/flash A/D converter. As shown therein, the conventional parallel/flash A/D converter includes a plurality of comparators
20
connected to each other in parallel. Each of the comparators
20
includes a negative terminal (−) for receiving an external analog signal V
1
, and a positive terminal (+) for receiving a reference voltage signal V
R1
-V
R(2
n
−1)
. Each comparator
20
compares the analog signal V
1
with the corresponding reference voltage V
R1
-V
R(2
n
−1)
, and outputs the comparison result to a decoder
21
. The decoder
21
decodes the signals received from the comparators
20
and outputs an N-bit digital signal.
Referring to
FIG. 2
, an operation of the conventional parallel/flash A/D converter will be described. As shown therein, each of the comparators
20
compares the external analog signal V
1
with the corresponding reference voltage V
R1
-V
R(2
n
−1)
and outputs a resultant value to the decoder
21
. The decoder
21
then decodes the signals output from each of the comparators
20
and outputs an N-bit digital signal. Here, the comparators
20
and the decoder
21
are driven by one clock signal output from a clock generator (not shown).
As described above, the analog signal V
1
input to the conventional A/D converter is sampled through the comparison operations of the comparators
20
in accordance with one preset voltage level, i.e., a reference voltage. The decoder
21
converts the sampled analog signal into a digital signal of N-bit, and outputs the digital signal representative of the analog signal V
1
.
In order to generate a digital signal which is more precise than the digital signal generated by the conventional A/D converters (for example, about twice as precise as the above digital signal), as many as twice of the number of comparators used in the conventional A/D converters are needed to decrease a sampling interval. However, since the conventional A/D converters are driven by a single-phase clock signal, even with a large number of comparators, a precise digital signal may not be obtained. Further, use of a large number of comparators increases the cost of the conventional A/D converters.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a device and method for converting an analog signal into a digital signal using interleaving sampling and a two-phase clock generator.
It is another object of the present invention to provide a device and method for converting an analog signal into a digital signal using an N-phase clock generator for generating clock signals with N different phases.
It is further another object of the present invention to provide a device and method for generating a digital signal which has been converted from an analog signal with accuracy and precision.
To achieve the above and other objects, there is provided an A/D converter including an N-phase clock signal generator generating an N number of clock signals having N different phases, a control logic generating first, second and third control signals in accordance with the clock signals generated by the N-phase clock signal generator, a comparator unit comparing an analog signal input thereto with reference signals, a transmission unit transmitting signals output from the comparator unit in accordance with the first and second control signals, and a decoding unit decoding the signals transmitted from the transmission unit in accordance with the third control signal.
Further, there is provided a method of converting an analog signal to a digital signal, including the steps of generating an N number of clock signals having N different phases, generating first, second and third control signals in accordance with the generated clock signals, comparing an analog signal with reference voltage signals, generating comparison signals based on comparison results, transmitting the comparison signals in accordance with the generated first and second control signals, and decoding the signals transmitted from said transmitting step in accordance with the generated third control signal.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed descriptions.
Additional advantages, objects and features of the invention will become more apparent from the description which follows.


REFERENCES:
patent: 4968988 (1990-11-01), Miki et al.
patent: 5302869 (1994-04-01), Hosotani et al.
patent: 5448239 (1995-09-01), Blumberg et al.
patent: 5534864 (1996-07-01), Ono et al.
patent: 5680133 (1997-10-01), Komatsu
patent: 5856800 (1999-06-01), Le Pailleur et al.
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