Electric power conversion systems – Current conversion – With voltage multiplication means
Reexamination Certificate
2001-10-12
2004-06-01
Vu, Bao Q. (Department: 2838)
Electric power conversion systems
Current conversion
With voltage multiplication means
C307S110000, C327S537000
Reexamination Certificate
active
06744646
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage regulating device. More particular, the present invention relates to a voltage regulating device that is implemented by a low voltage CMOS manufacturing process and capable of enduring a high voltage output.
2. Description of the Related Art
Due to highly developed technology of VLSI process for CMOS devices, the sizes of transistors become more compact and their operation voltage are also considerably reduced. However, due to specification and noise margin, voltage signals outputted from an IC chip are usually higher than voltage signals inside the IC chip when the voltage signals are transmitted between IC chips. For example, the voltage signals inside the IC chip may be 0V~1.5V, but its output voltage signals may be 0V~2.5V. Accordingly, in practice, it needs a voltage level regulator to regulate lower voltage signals (such as 0V~1.5V) inside the IC chips into higher voltage signals (such as 0V~2.5V).
Generally speaking, transistors made by more advanced CMOS manufacturing process, the voltage endured between two electrodes of the transistor becomes lower and lower. Namely, the operation voltage between the gate and source (V
GS
), or the operation voltage between the gate and drain (V
GD
) falls with a lower voltage range. Therefore, it must use a transistor that can be operated in higher voltages, such as a dual-gate transistor, during the voltage regulating process from lower voltage signals to higher voltage signals. However, the transistors having higher operation voltages usually consume more powers and heats. In order to improve such defects, a voltage level regulating device made by the low voltage CMOS manufacturing process, as shown in
FIG. 1
, is provided such that V
GS
and V
GD
of each transistor are in the accessible range of the low voltage CMOS manufacturing process and the chip can output high voltages.
FIG. 1
shows an output stage of an I/O circuit according to a conventional art. Referring to
FIG. 1
, the voltage signal in the IC chip is a low voltage signal
130
having a range of 0V~V
DD
, and V
DD
is 1.5V for example. The output voltage of the chip is 0V~V
CC
, and V
CC
is 2.5V for example, wherein V
CC
>V
DD
>V
CC
/2. In practice, voltage V
CC
is greater than maximum endurable voltage for voltages V
GS
, V
GD
of the transistor in the low voltage CMOS manufacturing process. Preventing transistors from damage, it must envisage the voltage endurance issues to improve circuit structure. According to the conventional method, gates of two transistors MPC and MNC are biased at V
CC
/2 and both interposed between transistors MPD and MND that serve as an output stage for an I/O circuit, wherein V
CC
/2 is less than maximum endurable voltage for voltages V
GS
, V
GD
of the transistor in the low voltage CMOS manufacturing process.
FIG. 1
shows two voltage level regulating device, one of which is a voltage level rising regulator
110
and the other is voltage level lowering regulator
120
. The voltage level rising regulator
110
is used for regulating the voltage signals inside the IC chip from 0V~V
CC
to V
CC
~V
CC
/2 and then transmitting them to the gate of the transistor MPD, while the voltage level lowering regulator
120
is used for regulating the voltage signals inside the IC chip from 0V~V
CC
to V
CC
/2~0 and then transmitting them to the gate of the transistor MND. Accordingly, the voltages V
GS
and V
GD
of the transistors MPD, MND, MPC and MNC can be controlled without exceeding V
CC
/2, for preventing the transistors from damages due to high operation voltages.
When the voltage signal inside the IC chip is 0V, the output voltage V
CC
of the voltage level rising regulator
110
causes the transistors MPD, MPC to be turned off and the output voltage V
CC
/2 of the voltage level lowering regulator
120
causes the transistors MND, MNC to be turned on, by which the output voltage of the IC chip becomes 0V. In contrast, when the voltage signal inside the IC chip is V
DD
, the output voltage V
CC
/2 of the voltage level rising regulator
110
causes the transistors MPD, MPC to be turned on and the output voltage 0V of the voltage level lowering regulator
120
causes the transistors MND, MNC to be turned off, by which the output voltage of the IC chip becomes V
CC
.
As described above, when the voltage signal inside the IC chip is 0V, the IC chip outputs a voltage of 0V, and when the voltage signal inside the IC chip is V
DD
, the IC chip outputs a voltage of 0V
CC
. Therefore, it can be learned that the voltage level rising regulator
110
is used for converting the low voltage signal
130
into a high voltage signal
140
having a range of V
CC
~V
CC
/2, while the voltage level lowering regulator
120
is used for converting the low voltage signal
130
into a lower voltage signal having a range of V
CC
/2~0V.
FIG. 2
shows the function of the voltage level rising regulator. The voltage level rising regulator
110
can covert the low voltage signal
130
into the high voltage signal
140
, in which the low voltage signal
130
is between a low level
131
of the low voltage signal
130
and a high level
135
of the low voltage signal
130
and the high voltage signal
140
is between a low level
141
of the high voltage signal
140
and a high level
145
of the high voltage signal
140
. For example, the low voltage signal
130
can the voltage signal inside the IC chip, and low level
131
is 0V, the high level
135
is V
DD
, the high voltage signal
140
is the output of voltage level rising regulator
110
, the low level
141
is V
CC
/2, and the high level
145
is V
CC
.
It should be noted that voltage level rising regulator
110
is implemented by the low voltage CMOS manufacturing process and output voltages of V
CC
~V
CC
/2. However, V
CC
has exceeded the voltage endurances for V
GS
, V
GD
of the low voltage CMOS manufacturing process. During circuit design, it must guarantee that V
GS
, V
GD
of each transistor in voltage level rising regulator
110
are operated within an allowable voltage range in order that the circuit can be normally worked. Therefore, one of solutions for solving this issue, shown in
FIG. 3
, is provided.
FIG. 3
shows a conventional voltage level rising regulator, which is published on IEEE JSSC, November, 1999. Metal-oxide-semiconductor (MOS) transistor is extensively used in integrated circuits and it usually uses PMOS to denote a P-type MOS transistor and NMOS to denote a N-type MOS transistor. According to the disclosure, the maximum voltage endurance is 2.4V for V
GS
and V
GD
of the CMOS transistors. When the voltage V
DD
of the output stage of the I/O circuit is 3.3V , the amplitude of input voltage of the voltage level rising regulator is 0V~1.8V. The pbias terminal voltage is 1.1V, the pdrive output voltage is 3.3V~(1.1+V
tp
), wherein is the threshold voltage of PMOS transistors TP
3
, TP
4
, and the en
18
_buffered voltage is 0V.
When the gate voltage of the transistor TN
1
is 1.8V, voltages at nodes node
1
and node
2
are 0V. Theoretically, because the transistor TP
3
is biased at pbias, the terminal voltage of pdrive is pulled down to pbias +V
tp
. Considering the subthreshold leakage and well leakage, the terminal voltage of pdrive is perhaps pulled down to 0, and then V
GS
of the transistors Tp
1
and TP
2
exceeds maximum endurable voltage drop 2.4V. Therefore, a transistor TP
5
is used for pulling up current, for avoiding voltage pdrive from dropping below pbias. When the voltage fed to the transistor TN
1
is 0V, the voltages at node node
2
and node
4
become 0V. As a result, voltage pdrive is pulled down to pbias +V
tp
to turn on the transistor TP
1
and then pulls the voltage pdrive up to 3.3V.
Accordingly, in the conventional circuit, the transistors TP
3
, TP
4
are used to avoid transistors TP
1
, TP
2
from operating under high V
GS
and V
GD
. Similarly, the transistors TN
3
, TN
4
are used to avoid transistors TN
1
, TN
2
from operating under hi
Huang Jin-Cheng
Huang Yen-Mou
Rabin & Berdo P.C.
Via Technologies Inc.
Vu Bao Q.
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