Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-06-05
2003-01-07
Oda, Christine (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S522000
Reexamination Certificate
active
06504380
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of integrated circuits, and, more particularly, to the checking of integrated capacitors, such as for matching and linearity. Moreover, the invention advantageously, but not exclusively, applies to the checking of the quality of capacitors of mass-produced integrated circuits. Further, the invention also relates to analog-digital converters using switched capacitors.
BACKGROUND OF THE INVENTION
An integrated circuit including, for example, a switched-capacitor analog-digital converter may include a certain number of capacitors which in theory are identical in their capacitive values. However, once the integrated circuit has been produced on silicon, these theoretically identical capacitors have in practice slightly different actual characteristics. These actual characteristics result in matching defects, i.e., there are differences between their respective actual capacitive values.
Such matching defects are due, for example, to plate surface areas which differ slightly from one capacitor to another or to differences in permittivity of the dielectrics from one capacitor to another. The causes of these differences are generally associated with the inevitable variations in the fabrication process (non-uniform quality of the oxide deposited, use of a plasma, location of the capacitors on the wafer, etc.).
These same variations may result in capacitors which display linearity defects, generally due to the quality of the dielectric. Those of skill in the art will appreciate that non-linearity of a capacitor results in a capacitive value which depends upon the voltage applied at its terminals, whereas in theory a capacitor is “linear,” i.e., its capacitive value is independent from the voltage applied at its terminals.
At the present time, there are statistical laws which make it possible to determine the matching defects for pairs of adjacent capacitors. However, a simple way of checking the characteristics of capacitors produced while simultaneously determining the matching and linearity defects of theoretically identical integrated capacitors is not currently known.
SUMMARY OF THE INVENTION
An object of the invention is to provide a relatively simple method for checking capacitors.
Another object of the invention is to provide a system for determining the matching defect and the non-linearity of theoretically identical integrated capacitors, such as using a single decisional parameter which may be likened to a resolution in terms of number of bits.
Yet another object of the invention is to provide a system for quickly and efficiently checking the matching defect and the non-linearity of theoretically identical capacitors of integrated circuits mass-produced on a semiconductor wafer.
Still another object of the invention is to determine relatively simply the actual maximum resolution of analog-digital converters produced on integrated circuits.
A further object of the invention is to provide a reference voltage generator for analog-digital converters which is particularly robust and precise.
These and other objects, features, and advantages according to the invention are provided by a device for checking theoretically identical integrated capacitors, the device including a capacitive structure including an input node and n output nodes, n being an integer greater than or equal to 2. The capacitive structure also includes r integrated capacitors connected in series between two adjacent nodes, r being an integer greater than or equal to 1.
The capacitive structure may also include an integrated capacitor connected between the input node and ground and an integrated capacitor connected between the nth output node and ground. Furthermore, the capacitive structure may include r capacitive branches connected in parallel between ground and each node of the capacitive structure including the first output node and the (n−1)th output node. Each branch includes r+1 series-connected integrated capacitors. All the capacitors of the capacitive structure are theoretically identical.
The checking device may include, in addition to the capacitive structure, charging means capable of charging each node of the capacitive structure, measurement means capable of measuring the charge at each of the nodes of the structure, and comparison means capable of comparing each measured nodal charge value with a theoretical nodal charge value, taking into account a predetermined nodal tolerance. Although r can in theory take an integer value greater than or equal to 1, it is particularly beneficial to choose r=1, thereby making it possible to obtain a ratio of 2 between the voltages present at two adjacent nodes of the capacitive structure. This is particularly well suited to analog-digital conversion.
The charging means may include a reference voltage source and a controllable switch connected between the voltage source and the input node. Further, the measurement means may include, for each node of the capacitive structure, a controllable measurement switch connected to the node and an ammeter capable of being connected between the measurement switch and ground. The use of an ammeter for measuring a charge at each of the nodes of the capacitive structure is particularly advantageous compared with measuring voltages at the terminals of capacitors. This is because a voltmeter has parasitic capacitances which may falsify the measurement.
Advantageously, the device may also include a controllable discharge switch for each node of the capacitive structure connected between the node and ground. This makes it possible to discharge all the capacitors before taking the measurement.
The device according to the invention may advantageously be used for checking integrated capacitors of an integrated circuit on a die of a semiconductor wafer and bounded by dicing streets formed in the wafer. Advantageously, the capacitive structure is then inserted into one of the dicing streets by which the die is bounded. The plate surface area of the capacitors of the capacitive structure is then chosen to be at most equal to the minimum plate surface area of the capacitors of the integrated circuit.
In other words, if the integrated circuit includes capacitors of the same plate surface area, for example, a capacitive structure including capacitors of identical plate surface area will then be chosen. However, if the integrated circuit includes capacitors having different plate surface areas (e.g., one group of capacitors having a first predetermined plate surface area and another group of capacitors having a second plate surface area equal to half the first plate surface area), then a capacitive structure will be chosen whose capacitors have a plate surface area equal to the second plate surface area. This is because the greater the plate surface area of the capacitors, the better the matching between these capacitors. Thus, if the checking device of the invention results in matching that is acceptable for capacitors having the minimum surface area, the same will apply a fortiori to capacitors having a larger surface area.
The capacitive structure of the device according to the invention may also be used as a reference voltage or charge generator for a switched-capacitor analog-digital converter. In this case, a voltage source is connected to the input node. The various reference voltages or charges are then available at the various nodes (which are output nodes) of the capacitive structure, respectively. The use of such a capacitive structure for switched-capacitor analog-digital converters is particularly advantageous because it is, by nature, less sensitive to the matching defects of the capacitors as well as their linearity defects.
The invention also relates to a method of checking theoretically identical integrated capacitors in a capacitive structure which includes an input node and n output nodes (n being an integer greater than or equal to 2), and r integrated capacitors connected in series between two adjacent nodes (r being an integer greater than or
Bianchi Raul Andres
Froment Benoît
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
He Amy
Jorgenson Lisa K.
Oda Christine
STMicroelectronics S.A.
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