Static information storage and retrieval – Addressing – Sync/clocking
Patent
1997-11-28
1999-03-09
Le, Vu. A.
Static information storage and retrieval
Addressing
Sync/clocking
36518901, G11C 700
Patent
active
058810188
ABSTRACT:
A device and a method for automatically setting a status of a dynamic random access memory through the control of a clock enable signal. The device comprises a frequency amplification circuit for amplifying a main clock signal by a desired number of times in response to a frequency amplification enable signal and outputting the amplified signal as an internal clock signal, a clock enable detection/control circuit for detecting the clock enable signal, combining the detected clock enable signal with the internal clock signal from the frequency amplification circuit to generate the frequency amplification enable signal, a memory status setting signal and a clock enable latch signal and outputting the frequency amplification enable signal to the frequency amplification circuit, and a status setting signal output circuit for generating a plurality of command signals in response to the memory status setting signal and clock enable latch signal from the clock enable detection/control circuit and outputting the generated command signals to the dynamic random access memory. According to the present invention, a mode of the memory can automatically be changed through the control of only the clock enable signal. This is convenient to the user.
REFERENCES:
patent: 4939470 (1990-07-01), Kang
patent: 5483496 (1996-01-01), Murakawa
patent: 5495451 (1996-02-01), Cho
patent: 5577005 (1996-11-01), Bae
Hyundai Electronics Industries Co,. Ltd.
Le Vu. A.
Nath Gary M.
Novick Harold L.
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