Device and a method for monitoring a system clock signal

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By presence or absence pulse detection

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327 21, 327 3, 327 18, 327 38, 327 31, 377 69, H03K 519

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active

059231912

ABSTRACT:
A system clock signal monitor that monitors a system clock signal by comparing a pulse width of a logic high pulse and a pulse width of a logic low pulse of each system clock duty cycle of the system clock signal to one or more reference clock duty cycles in order to detect any pulse width violations. For each system clock duty cycle, a pulse width violation is detected if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is equal to or greater than a maximum time interval for the logic high pulse and the logic low pulse. A pulse width violation may also occur if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is within a risk range (as defined by the system designer) of the maximum time interval for the logic high pulse and the logic low pulse. The system clock signal monitor can be further designed to warn/reset a processor or a user of the processor upon the detection of one or more detected occurrences of a pulse width violation.

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