Deterministic latency characterization and mitigation

Details Deterministic latency characterization and mitigation Deterministic latency characterization and mitigation

1996-09-26

1998-06-16

Harvey, Jack B.

395287, 395297, 395728, 395856, G06F 1314

Patent

active

057685444

ABSTRACT:
A method is provided of requesting use of a shared resource in a computer system. The method is suited to applications in which the device requesting use of the resource can predict the need for the resource before the need actually arises. A request for use of the resource is characterized by a latency between the request and a subsequent granting of the request. The latency has both a deterministic component and a non-deterministic component. In response to an initialization of the computer system, the deterministic component of the latency is measured. The use of the resource is then requested by the requesting device some predetermined time before the time at which the need for such use arises. The predetermined time corresponds to the deterministic component of the latency. The amount of local buffering required within the device is therefore chosen to accommodate only the random latency component.

REFERENCES:
patent: 5404464 (1995-04-01), Bennett
patent: 5537602 (1996-07-01), Kametani
patent: 5574868 (1996-11-01), Marisetty
patent: 5625778 (1997-04-01), Childers et al.
patent: 5664197 (1997-09-01), Kardach et al.
patent: 5680554 (1997-10-01), Baek
Institute of Electrical and Electronics Engineers P1394.2 Standard, "Serial Express A Scalabe Gigabit Extension to Serial Bus", Apr. 8, 1996.
ISO/IEC 13213, ANSI/IEEE Standard 1212, "Information technology-Microprocessor systems-Control and Status Registers (CSR) Architecture for microcomputer buses", Oct. 5, 1995, first edition, pp. 41-45.

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