Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
1998-11-02
2003-09-23
Banankhah, Majid (Department: 2127)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
C709S241000
Reexamination Certificate
active
06625635
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to computer systems, and more particularly to a method for deterministic and pre-emptive thread scheduling. Still more particularly, the present invention relates to a method for deterministic and pre-emptive thread scheduling utilized to support cyclical debugging of multithreaded applications.
2. Description of the Related Art
The basic structure of a conventional computer system includes a system bus or a direct channel that connects one or more processors to input/output (I/O) devices (such as a display monitor, keyboard and mouse), a permanent memory device for storing the operating system and user programs, (such as a magnetic hard disk), and a temporary memory device that is utilized by the processors to carry out program instructions (such as random access memory or “RAM”).
When a user program runs on a computer, the computer's operating system (OS) first loads the program files into system memory. The program files include data objects and instructions for handling the data and other parameters which may be input during program execution.
The operating system creates a process to run a user program. A process is a set of resources, including (but not limited to) values in RAM, process limits, permissions, registers, and at least one execution stream. Such an execution stream is commonly termed “thread.” The utilization of threads in operating systems and user applications is well known. Threads allow multiple execution paths within a single address space (the process context) to run concurrently on a processor. This “multithreading” increases throughput and modularity in multiprocessor and uniprocessor systems alike. For example if a thread must wait for the occurrence of an external event, then it stops and the computer processor executes another thread of the same or different computer program to optimize processor utilization. Multithreaded programs also can exploit the existence of multiple processors by running the application program in parallel. Parallel execution reduces response time and improves throughput in multiprocessor systems.
FIG. 1
illustrates multithreading in a uniprocessor computer system
10
, which includes a bus
18
that connects one processor
12
to various I/O devices
14
and a memory device
16
. Memory device
16
contains a set of thread context fields
20
, one for each thread associated with a particular process. Each thread consists of a set of registers and an execution stack
24
. The register values are loaded into the CPU registers when the thread executes. The values are saved back in memory when the thread is suspended. The code that the thread runs is determined by the contents of a program counter within the register set. The program counter typically points to an instruction within the code segment of the application program. Memory device
16
further contains all of the logical addresses for data and instructions utilized by the process, including the stacks of the various threads. After a thread is created and prior to termination, the thread will most likely utilize system resources to gain access to process context
22
. Through the process context
22
, process threads can share data and communicate with one another in a simple and straightforward manner.
Thread scheduling is an important aspect of implementing threads. In a first category, there are cooperative threads which do not rely on a scheduler and cooperate among themselves to share the CPU. Because of the complexities involved in programming such threads, and because they cannot react quickly to external events, cooperative threads are not utilized much in the art nowadays. In a second category are pre-emptive threads. Such threads rely on a scheduler that can decide to switch the CPU from one thread to another at any point during the execution. Pre-emptive threads react quickly to external events because the currently running thread could be pre-empted out of the CPU and another thread takes over to handle the emergency, if needed. Unlike cooperative threads, pre-emptive scheduling relieves the programmer from the burden of implementing the scheduling mechanism within the application program.
Pre-emption of a running thread can generally occur at any point during program execution. Typically, pre-emption occurs when a timer expires allowing the scheduler to intervene and switch the CPU among threads. In the art, this is referred to as “time slicing” the CPU among threads, and each thread is said to run for a “time slice.” This form of intervention allows the scheduler to implement various scheduling mechanisms, including round robin, priority scheduling, among others. Additionally, pre-emption could also occur in response to external events that may require the immediate attention of some thread.
However, when two copies of the same program run on two different machines, the timer interrupts do not preempt the threads at the same execution points because of the differences in the clock speeds of the two machines. This effect results in the threads potentially accessing shared memory in different orders on the two machines, yielding different results.
FIG. 2
illustrates this effect.
FIG. 2
shows what occurs when the same set of threads
32
are run on two different processors, Processor A
36
a
and Processor B
36
b,
utilizing time slicing. Processor A
36
a
runs at one clock speed and executes the threads as shown in Output A
38
a.
Processor B, runs at a slightly different clock speed and executes the threads as shown in Output B
38
b.
The processors yield different outputs from threads running identical programs. The output connected to “write X” will depend on which thread wrote to that variable last, and this is in turn varies depending on whether Processor A
36
a
or Processor B
36
b
is utilized. Thus, one “write X”
39
a
yields a different output from “write X”
39
b.
Similarly, the output of “write Y” differs between the two processors. Processor A
36
a
yields the value read during execution, while Processor B
36
b
yields an unknown value stored prior to the thread's execution. Such inconsistencies are common when utilizing time slices as done in the current art, making the current art incapable of supporting cyclical debugging of multithreaded applications. Cyclical debugging requires that two runs of the same program produce the same outputs and go through the same execution paths. In the example we have shown in
FIG. 2
, the two different results may correspond to two different runs on the same processor making debugging very difficult.
The result of the application program often depends on the exact points within the execution streams where pre-emptions occur. Therefore, pre-emptive thread scheduling in a multithread program is a source of nondeterminism that affects its final results. If a multithreaded application runs twice on the same machine, the threads may access shared memory in different orders to yield different results. Thus, even if the program starts with the same input on the same machine, two runs of the program may yield different results.
One method of debugging is discussed in a 1989 article by Mellor-Crummey and LeBlanc. The article, “A Software Instruction Counter,” describes a method for debugging utilizing a software instruction counter; however, unlike this invention, the article does not rely on any particular scheduling support, and assumes the utilization of timers. Thus, in their technique they generate a log record each time a timer expires, making the log size impracticably large. This invention solves this problem via an innovative scheduling mechanism that can also support efficient debugging and general purpose preemptive and deterministic scheduling, when such scheduling is needed.
It would therefore be desirable and advantageous to provide an improved method of cyclical debugging by scheduling of threads in a way which would be deterministic and preemptive.
SUMMARY OF THE INVENTION
It is the
Banankhah Majid
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Salys Casimer K.
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