Determining maximum load index for tabular timing models

Details Determining maximum load index for tabular timing models Determining maximum load index for tabular timing models

1996-12-17

1999-05-11

Teska, Kevin J.

Boots, shoes, and leggings

395500, G06F17/10

Patent

active

059034688

ABSTRACT:
In accordance with the preferred embodiment of the present invention, a logic cell library is built. Within the logic cell library a timing model for a first logic cell is generated. In order to generate the timing model a number of indices which specify input ramp for the first logic cell is selected. Also, a number of indices which specify output load for the first logic cell is selected. Also selected are a minimum value for the input ramp and a maximum value for the input ramp. A maximum output load for the timing model is calculated. This is done by calculating, for every input transition in the logic cell which causes an output transition, an intermediate value to be an output load value which results in the first logic cell producing an output signal to the first logic cell which has the maximum value for the input ramp when an input signal to the logic cell has the minimum value for the input ramp. The maximum output load is chosen to be a minimum of the calculated intermediate values.

REFERENCES:
patent: 5559715 (1996-09-01), Misheloff
patent: 5625803 (1997-04-01), McNelly et al.
R.W. Phelps, Advanced Library Characterization for High Performance ASIC, Proceedings of the IEEE International Asic Conference, 1991, pp. P15-3.1 through P15-3.4.
A. Martinez, Automated Library Characterization and Timing Model Accuracy Issues when Interfacing to Different CAD Tools, presented at the WG 10.5 IFIP Workshop on Synthesis, Generation, and Portability of Library Blocks for ASIC Design, Grenoble, France, Mar. 12-13, 1992.

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