Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification
Reexamination Certificate
2008-12-14
2011-11-08
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Analysis and verification
C716S056000
Reexamination Certificate
active
08056023
ABSTRACT:
The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask to determine a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has edges, and where each target edge pair is defined by two of the edges of one or more of the polygons. The number of the target edge pairs is reduced to decrease computational volume in determining the manufacturing penalty in making the lithographic mask. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined based on the target edge pairs as reduced in number. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.
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Inoue Tadanobu
Melville David O.
Muta Hidemasa
Rosenbluth Alan E.
Sakamoto Masahura
Aisaka Bryce
Alexanian Vazken
Dinh Paul
International Business Machines - Corporation
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