Determination of testability of combined logic end memory by ign

Details Determination of testability of combined logic end memory by ign Determination of testability of combined logic end memory by ign

1986-05-14

1988-02-16

Atkinson, Charles E.

Excavating

324 73R, 371 21, 371 25, G01R 3128

Patent

active

047260238

ABSTRACT:
A method of bounding, from above and below, the probability of uncovering a fault in a logic portion of an integrated circuit having embedded memory. The circuit must be designed according to a specified set of design rules. Then one or more probabilities of fault exposure is calculated for a modified system with the memory portion removed, with its inputs directly connected to its outputs. This probability can be related, by provided relations, to upper and lower bounds of the fault exposure in the unmodified system. The relationships rely upon how the logic portions process given test vectors to control the unremoved memory portion.

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