Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1988-12-28
1989-12-05
Heyman, John S.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307471, 307481, 307585, H03K 3013, H03K 524, H03K 17687, H03K 19096
Patent
active
048855448
ABSTRACT:
A coincidence determination circuit capable of reducing number of elements by providing a time period during which the coincidence determination is enabled. This coincidence determination circuit comprises, a first comparison unit provided with a plurality of first bit comparison units corresponding to a plurality of bits, each bit comparison unit comprising a first P-channel transistor having a gate to which a clock signal is inputted, a second P-channel transistor having a gate to which reference data of a certain bit is inputted, and a third P-channel transistor having a gate to which inverted data of the data of that bit to be compared is inputted, the first to third P-channel transistors being connected in series, respective outputs of the first bit comparison units being wired-OR connected to a first output line, said first output line serving to pull its signal level down in response to the clock signal; a second comparison unit provided with a plurality of second bit comparison units corresponding to a plurality of bits, each bit comparison unit comprising a first N-channel transistor having a gate to which an inverted signal of the clock signal is inputted, a second N-channel transistor having a gate to which reference data of a certain bit is inputted, and a third N-channel transistor having a gate to which inverted data of the data of that bit to be compared is inputted, the first to third N-channel transistors being connected in series, respective outputs of the second bit comparison units being wired-OR connected to a second output line, the second output line serving to pull its level up by the inverted signal of the clock signal; and an output unit for producing a coincidence output when the first output line is at a low level and the second output line is at a high level.
REFERENCES:
patent: 4694274 (1987-09-01), Shimada et al.
patent: 4710650 (1987-12-01), Shoji
patent: 4785204 (1988-11-01), Terada et al.
patent: 4797625 (1989-01-01), Nakazawa
patent: 4808855 (1989-02-01), Lloyd
"IBM Technical Disclosure Bulletin", vol. 27, No. 8, Jan. 1985, Lee et al, Low Device Count Clocked CMOS Exclusive OR Circuit.
Bertelson David R.
Heyman John S.
Kabushiki Kaisha Toshiba
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