Detector driven bias circuit for power transistors

Details Detector driven bias circuit for power transistors Detector driven bias circuit for power transistors

1999-06-10

2002-07-30

Bost, Dwayne (Department: 2681)

Telecommunications

Receiver or analog modulated signal frequency converter

Local control of receiver operation

C455S127500, C330S296000

Reexamination Certificate

active

06427067

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a power transistor, and more particularly, to a power transistor having a detector driven bias circuit that adjusts the gain of the power transistor in relation to the power level of an amplified signal.
BACKGROUND OF THE INVENTION
The base or gate bias of a known power transistor operating in an AB mode is provided by a constant voltage source. The constant voltage source applies a bias to the AB mode power transistor that is substantially constant at all signal levels. The bias of a known power transistor operating in an A mode is regulated at a constant level by a circuit control loop that monitors the average transistor current and applies a regulated bias current for biasing the transistor. The bias supplied to the A mode power transistor is substantially constant at all signal levels. For a circuit having a power transistor operating in Class AB mode, a small amount of quiescent current flows even in the absence of an RF signal to be amplified. For a circuit having a power transistor operating in Class A mode, the average current flow is substantially the same for all levels of RF signal to be amplified. Each known transistor has its base voltage, or gate voltage in the case of a field effect transistor, FET or low density metal oxide silicon transistor, LDMS transistor, held constant during power peaks.
It would be desirable to dynamically increase the gain of a power transistor beyond that which would be provided by a known power transistor that has a constant bias at all signal levels. Further, it would be desirable to provide a positive increase in the bias supplied to a power transistor, especially during power peaks, to increase the gain so that the gain is more constant with increasing instantaneous power, relative to the non-compensated circuit.
SUMMARY OF THE INVENTION
The invention is a circuit that detects the envelope of an incoming signal and increases the bias voltage approximately in proportion to the RF voltage of the incoming signal, which increases the gain, particularly at levels of relative peak power. The increase in gain compensates for the normal decrease in gain that the transistor has as its compression point is reached. The decrease in gain is not so much a problem of decreased output as it is a problem of distortion. This distortion is a result of having an undesired signal dependent gain, which makes the transistor nonlinear. The invention reduces the cost per watt of power, particularly at rf, radio frequencies, and is further applicable to reduce the cost per watt of power at other signal frequencies, such as, baseband, video and audio frequencies. This reduction in cost is based on the idea that a smaller device can be used whose total distortion is the same as a larger device with no correction.
Unlike the known circuits in which the base voltage of a transistor is held constant, or the gate voltage for FETs and LMDS power transistors is held constant, especially during power peaks, the invention provides an increase in the base voltage or the gate voltage to increase the instantaneous gain. Further the invention increases the base voltage or the gate voltage approximately proportional to the signal, which increases the gain during power peaks. The effect of the invention in the case of the AB circuit is to push the compression point of the transistor up by approximately 0.5 dB, and more, and to reduce the intermods for a high peak factor signal by typically 3 to 4 dB. The effect of the invention in the case of the Class A circuit is to effectively increase the third order intercept point (IP
3
) of a given device by as much as 6 dB. Alternatively, a given IP
3
performance can be obtained by using a device of half the size/cost, at half the current, in the case of Class A operation. This allows the circuit to obtain the highest compression point for a given cost of the transistor and, in the case of the Class A circuit, for a given current level. The increased compression point, as provided by the invention, is further advantageous to reduce the level of intermodulation signals and spectral regrowth, as the invention maintains low distortion
Embodiments of the invention will be described by way of example, with reference to the accompanying drawings.


REFERENCES:
patent: 3720880 (1973-03-01), Le Seigneur
patent: 4317083 (1982-02-01), Boyd
patent: 4665560 (1987-05-01), Lange
patent: 4736391 (1988-04-01), Siegel
patent: 6052032 (2000-04-01), Jarvinen
patent: 6304145 (2001-10-01), Laureanti et al.
patent: 6313705 (2001-11-01), Dening et al.
“Methods Linearize RF Transmitters And Power Amps”,Microwaves&RF, Dec. 1998, pp. 102-110.
“Device And Circuit Approaches For Next-Generation Wireless Communications”,Microwave Journal, Feb. 1999, pp. 22-42.

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